HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 36

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

AC Electrical Specifications
NOTES:
10. I
11. TX_PE must be inactive before going active to generate a new packet.
12. I
13. RX_PE must be inactive at least 3 MCLKs before going active to start a new CCA or acquisition.
14. RX_PE active to inactive delay to prevent next RX_CLK.
15. Assumes RX_PE inactive after last RX_CLK.
16. MD_RDY programmed to go active after SFD detect. (Measured from I
17. MD_RDY programmed to go active at MPDU start. Measured from first chip of first MPDU symbol at I
18. Minimum time to ensure Reset. RESET must be followed by an RX_PE pulse to ensure proper operation. This pulse should not be used for first
19. Delay from TXCLK to inactive edge of TXPE to prevent next TXCLK. Because TXPE asynchronously stops TXCLK, TXPE going inactive within
TX_CLK to TX_PE Inactive (11Mbps)
TX_RDY Inactive to Last Chip of MPDU Out
TXD Modulation Extension
RX_PE Inactive Width
RX_CLK Period (11Mbps Mode)
RX_CLK Width Hi or Low (11Mbps Mode)
RX_CLK to RXD
MD_RDY to 1st RX_CLK
RXD to 1st RX_CLK
Setup RXD to RX_CLK
RX_CLK to RX_PE Inactive (1Mbps)
RX_CLK to RX_PE Inactive (2Mbps)
RX_CLK to RX_PE Inactive (5.5Mbps)
RX_CLK to RX_PE Inactive (11Mbps)
RX_PE inactive to MD_RDY Inactive
Last Chip of SFD in to MD_RDY Active
RX Delay
RESET Width Active
RX_PE to CCA Valid
RX_PE to RSSI Valid
SCLK Clock Period
SCLK Width Hi or Low
Setup to SCLK + Edge (SD, SDI, R/W, CS)
Hold Time from SCLK + Edge (SD, SDI, R/W, CS)
SD Out Delay from SCLK + Edge
SD Out Enable/Disable from R/W
TEST 0-7, CCA, ANTSEL, TEST_CK from MCLK
7. AC tests performed with C
8. Not tested, but characterized at initial design and at major process/design changes.
9. Measured from V
V
receive or acquisition.
40ns of TXCLK will cause TXCLK minimum hi time to be less than 40ns.
OUT
OUT
OH
/Q
/Q
= V
OUT
OUT
OL
= V
are modulated before first valid chip of preamble is output to provide ramp up time for RF/IF circuits.
are modulated after last chip of valid data to provide ramp down time for RF/IF circuits.
CC
IL
/2.
PARAMETER
to V
IH
.
L
= 40pF, I
36
V
OL
CC
= 2mA, and I
= 3.0V to 3.3V ±10%, T
OH
= -1mA. Input reference level all inputs V
HFA3863
SYMBOL
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCED
A
t
t
t
t
t
t
t
t
t
RPW
SCW
t
RCP
RCD
RDD
RDS
REH
REH
REH
REH
CCA
CCA
SCH
SCD
PEH
RLP
RD1
RD1
RD2
RD3
SCP
SCS
t
t
ME
D2
RI
= -40
IN
o
C to 85
, Q
IN
.)
o
C (Note 8) (Continued)
2.77
2.77
MIN
940
940
-20
70
90
44
25
31
50
90
20
30
0
2
0
0
0
0
5
0
-
-
-
-
-
MCLK = 44MHz
CC
/2. Test V
IN
, Q
IN
MAX
2.86
2.86
800
925
380
140
65
60
50
30
16
16
30
15
40
to MD_RDY active.
-
-
-
-
-
-
-
-
-
-
-
-
IH
= V
CC
, V
IL
= 0V;
ns (Note, 19)
µs (Note 12)
ns (Note 13)
ns (Note 16)
ns (Note 14)
ns (Note 14)
ns (Note 14)
ns (Note 14)
ns (Note 15)
µs (Note 16)
µs (Note 17)
ns (Note 18)
UNITS
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns