HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 5

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

Control Port (4 Wire)
The serial control port is used to serially write and read
data to/from the device. This serial port can operate up to a
11MHz rate or 1/2 the maximum master clock rate of the
device, MCLK (whichever is lower). MCLK must be running
and RESET must be inactive during programming. This
port is used to program and to read all internal registers.
The first eight bits always represent the address followed
immediately by the eight data bits for that register. The LSB
of the address is a don’t care, but reserved for future
NOTES:
REFERENCE
1. The HFA3863 always uses the rising edge of SCLK to sample address and data and to generate read data.
2. These figures show the controller using the falling edge of SCLK to generate address and data and to sample read data.
ANT_SEL
SIGNALS
ANALOG
INPUTS
POWER
DOWN
PORT
TEST
A/D
FIGURE 1. EXTERNAL INTERFACES
8
SCLK
SCLK
RXI
RXQ
AGC
V
I
TX_PE
RX_PE
RESET
TEST
REF
R/W
R/W
REF
SD
CS
SD
CS
HFA3863
5
MD_RDY
TX_RDY
TXCLK
MSB
MSB
7
SCLK
7
7
AGC
7
TXQ
RXD
RXC
TXD
R/W
SDI
TXI
CS
SD
6
6
6
FIRST ADDRESS BIT
6
5
5
ADDRESS IN
5
5
ADDRESS IN
FIGURE 3. CONTROL PORT WRITE TIMING
FIGURE 2. CONTROL PORT READ TIMING
ANALOG
OUTPUTS
TX_PORT
RX_PORT
CONTROL_PORT
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
HFA3863
0
0
0
MSB
7
MSB
7
FIRST DATABIT OUT
7
7
6
6
expansion. The serial transfers are accomplished through
the serial data pin (SD). SD is a bidirectional serial data
bus. Chip Select (CS), and Read/Write (R/W) are also
required as handshake signals for this port. The clock used
in conjunction with the address and data on SD is SCLK.
This clock is provided by the external source and it is an
input to the HFA3863. The timing relationships of these
signals are illustrated in Figures 2 and 3. R/W is high when
data is to be read, and low when it is to be written. CS is an
asynchronous reset to the state machine. CS must be
active (low) during the entire data transfer cycle. CS selects
the serial control port device only. The serial control port
operates asynchronously from the TX and RX ports and it
can accomplish data transfers independent of the activity at
the other digital or analog ports.
The HFA3863 has 96 internal registers that can be
configured through the control port. These registers are
listed in the Configuration and Control Internal Register
table. Table 10 lists the configuration register number, a
brief name describing the register, the HEX address to
access each of the registers and typical values. The type
indicates whether the corresponding register is Read only
(R) or Read/Write (R/W). Some registers are two bytes
wide as indicated on the table (high and low bytes).
6
6
5
5
DATA OUT
5
5
DATA IN
4
4
4
4
3
3
3
3
2
2
2
2
1
1
1
1
LSB
0
LSB
0
0
0