HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 8

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

Power Down Modes
The power consumption modes of the HFA3863 are
controlled by the following control signals.
Receiver Power Enable (RX_PE, pin 61), which disables the
receiver when inactive.
Transmitter Power Enable (TX_PE, pin 62), which disables
the transmitter when inactive.
Reset (RESET, pin 63), which puts the receiver in a sleep
mode. The power down mode where, both RESET and
RX_PE are used is the lowest possible power consumption
mode for the receiver. Exiting this mode requires a
maximum of 10 µs before the device is operational.
The contents of the configuration registers are not effected
by any of the power down modes. No reconfiguration is
required when returning to operational modes. Activation of
RESET does not corrupt learned values of AGC settings and
noise floor values.
Table 3 describes the power down modes available for the
HFA3863 (V
other inputs to the part (MCLK, SCLK, etc.) continue to run
except as noted.
SLEEP
STANDBY
TX
RX
NO CLOCK
MODE
CC
Inactive
Inactive
Inactive
RX_PE
Active
= 3.3V). The table values assume that all
I
CC
Standby
Inactive
Inactive
Inactive
TX_PE
Active
HFA3683
8
Inactive
Inactive
Inactive
RESET
Active
Active
44MHz
1.5mA
300 µA
15mA
50mA
1mA
HFA3783
AT
TABLE 3. POWER DOWN MODES
FIGURE 6. AGC CIRCUIT
Both transmit and receive functions disabled. Device in sleep mode. Control
Interface is still active. Register values are maintained. Device will return to its active
state within 10 µs.
Both transmit and receive operations disabled. Device will resume its operational
state within 1 µs of RX_PE or TX_PE going active.
Receiver operations disabled. Receiver will return in its operational state within 1 µs
of RX_PE going active.
Transmitter operations disabled. Transmitter will return to its operational state within
2 MCLKs of TX_PE going active.
All inputs at V
HFA3863
RX_RF_AGC
RX_IF_DET
RX_IF_AGC
RX_Q±
RX_I±
CC
Transmitter Description
The HFA3863 transmitter is designed as a direct sequence
spread spectrum phase shift keying (DSSS PSK) modulator.
It can handle data rates of up to 11Mbps (refer to AC and DC
specifications). The various modes of the modulator are
differential binary phase shift keying (DBPSK) for 1Mbps,
differential quaternary phase shift keying (DQPSK) for
2Mbps, and complementary code keying (CCK) for 5.5Mbps
and 11Mbps. These implement data rates as shown in Table
4. The major functional blocks of the transmitter include a
network processor interface, DPSK modulator, high rate
modulator, a data scrambler and a spreader, as shown in
Figure 7. CCK is essentially a quadra-phase form of M-ARY
Orthogonal Keying. A description of that modulation can be
found in Chapter 5 of: Telecommunications System
Engineering, by Lindsey and Simon, Prentis Hall publishing.
The preamble is always transmitted as the DBPSK
waveform while the header can be configured to be either
DBPSK, or DQPSK, and data packets can be configured for
DBPSK, DQPSK, or CCK. The preamble is used by the
receiver to achieve initial PN synchronization while the
header includes the necessary data fields of the
communications protocol to establish the physical layer
link. The transmitter generates the synchronization
preamble and header and knows when to make the DBPSK
to DQPSK or CCK switchover, as required.
or GND.
THRESH.
DETECT
HFA3863
Q ADC
I ADC
DAC
IF
1
1
7
6
6
DEVICE STATE
DEMOD
AGC
CTL
I/O
DATA I/O