HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 3

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

Pin Descriptions
V
GNDd (Digital) 1, 7, 36, 43,
V
RX_RF_AGC
RX_IF_AGC
TX_AGC_IN
TX_IF_AGC
RX_IF_DET
DDA
DDD
TX_RDY
ANTSEL
ANTSEL
(Analog)
RXQ, ±
TXCLK
RXCLK
TX_PE
NAME
GNDa
RXI, ±
V
I
CCA
RXD
TXD
REF
REF
(Analog)
(Digital) 2, 8, 37, 41,
12, 17, 22,
9, 15, 20,
25, 28
10/11
13/14
PIN
31
57
56
16
21
39
40
19
34
38
18
35
62
58
55
59
60
53
52
TYPE I/O
Ground
Ground
3
Power
Power
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
DC power supply 2.7V–3.6V (not hard wired together on chip).
DC power supply 2.7–3.6V.
DC power supply 2.7–3.6V, ground (not hard wired together on chip).
DC power supply 2.7–3.6V, ground.
Voltage reference for A/D’s and D/A’s.
Current reference for internal ADC and DAC devices. Requires a 12k Ω resistor to ground.
Analog input to the internal 6-bit A/D of the In-phase received data. Balanced differential 10+/11-.
Analog input to the internal 6-bit A/D of the Quadrature received data. Balanced differential 13+/14-.
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 40) for
differential drive of antenna switches.
The antenna select signal changes state as the receiver switches from antenna to antenna during the
acquisition process in the antenna diversity mode. This is a complement for ANTSEL (pin 39) for
differential drive of antenna switches.
Analog input to the receive power A/D converter for AGC control.
Analog drive to the IF AGC control.
Drive to the RF AGC stage attenuator. CMOS digital.
Input to the transmit power A/D converter for transmit AGC control.
Analog drive to the transmit IF power control.
When active, the transmitter is configured to be operational, otherwise the transmitter is in standby
mode. TX_PE is an input from the external Media Access Controller (MAC) or network processor to
the HFA3863. The rising edge of TX_PE will start the internal transmit state machine and the falling
edge will initiate shutdown of the state machine. TX_PE envelopes the transmit data except for the
last bit. The transmitter will continue to run for 4 µ s after TX_PE goes inactive to allow the PA to
shutdown gracefully.
TXD is an input, used to transfer MAC payload data unit (MPDU) data from the MAC or network
processor to the HFA3863. The data is received serially with the LSB first. The data is clocked in the
HFA3863 at the rising edge of TXCLK.
TXCLK is a clock output used to receive the data on the TXD from the MAC or network processor to
the HFA3863, synchronously. Transmit data on the TXD bus is clocked into the HFA3863 on the rising
edge. The clocking edge is also programmable to be on either phase of the clock. The rate of the clock
will be dependent upon the data rate that is programmed in the signalling field of the header.
TX_RDY is an output to the external network processor indicating that preamble and header
information has been generated and that the HFA3863 is ready to receive the data packet from the
network processor over the TXD serial bus.
Clear channel assessment (CCA) is an output used to signal that the channel is clear to transmit. The
CCA may be configured to one of four possible algorithms. The CCA algorithm and its features are
described elsewhere in the data sheet.
Logic 0 = Channel is clear to transmit.
Logic 1 = Channel is NOT clear to transmit (busy).
This polarity is programmable and can be inverted.
RXD is an output to the external network processor transferring demodulated header information and
data in a serial format. The data is sent serially with the LSB first. The data is frame aligned with
MD_RDY.
RXCLK is the bit clock output. This clock is used to transfer header information and payload data
through the RXD serial bus to the network processor. This clock reflects the bit rate in use. RXCLK is
held to a logic “0” state during the CRC16 reception. RXCLK becomes active after the SFD has been
detected. Data should be sampled on the rising edge. This polarity is programmable and can be
inverted.
HFA3863
DESCRIPTION