HFA3863IN96 Intersil Corporation, HFA3863IN96 Datasheet - Page 7

• Manufacturer Part Number: HFA3863IN96
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor with Rake Receiver and Equalizer, Tape And Reel
• Manufacturer: Intersil Corporation

RXCLK is an output from the HFA3863 and is the clock for
the serial demodulated data on RXD. MD_RDY is an output
from the HFA3863 and it may be set to go active after the
SFD or CRC fields. Note that RXCLK becomes active after
the start frame delimiter (SFD) to clock out the Signal,
Service, and Length fields, then goes inactive during the
header CRC field. RXCLK becomes active again for the
data. MD_RDY returns to its inactive state after RX_PE is
deactivated by the external controller, or if a header error is
detected. A header error is either a failure of the CRC
check, or the failure of the received signal field to match
one of the four programmed signal fields. For either type of
header error, the HFA3863 will reset itself after reception of
the CRC field. If MD_RDY had been set to go active after
CRC, it will remain low.
MD_RDY and RXCLK can be configured through CR 1, bits
1 and 0 to be active low, or active high. The receive port is
completely independent from the operation of the other
interface ports including the TX port, supporting therefore a
full duplex mode.
RX I/Q A/D Interface
The PRISM baseband processor chip (HFA3863) includes
two 6-bit analog to digital converters (A/Ds) that sample the
balanced differential analog input from the IF down converter
device (HFA3783). The I/Q A/D clock, samples at twice the
chip rate with a nominal sampling rate of 22MHz.
The interface specifications for the I and Q A/Ds are listed in
Table 2. The HFA3863 is designed to be DC coupled to the
HFA3783.
The voltages applied to pin 16, V
the references for the internal I and Q A/D converters. In
addition, For a nominal I/Q input of 400mV
suggested V
Full Scale Input Voltage (V
Input Bandwidth (-0.5dB)
Input Capacitance (pF)
Input Impedance (DC)
f
S
(Sampling Frequency)
PARAMETER
REF
TABLE 2. I, Q, A/D SPECIFICATIONS
voltage is 1.2V.
P-P
)
7
REF
0.90
MIN
5k Ω
-
-
-
and pin 21, I
11MHz
22MHz
P-P
TYP
1.00
2
-
, the
REF
MAX
1.10
set
-
-
-
-
HFA3863
AGC Circuit
The AGC circuit is designed to adjust for signal level
variations and optimize A/D performance for the I and Q
inputs by maintaining the proper headroom on the 6-bit
converters. There are two gain stages being controlled. At
RF, the gain control is a 30dB step change. This RF gain
control optimizes the receiver dynamic range when the
signal level is high and maintains the noise figure of the
receiver when it is needed most at low signal level. At IF the
gain control is linear and covers the bulk of the gain control
range of the receiver.
The AGC loop is partially digital which allows for holding the
gain fixed during a packet. The AGC sensing mechanism
uses a combination of the I and Q A/D converters and the
detected signal level in the IF to determine the gain settings.
The A/D outputs are monitored in the HFA3863 for the
desired nominal level. When it is reached, by adjusting the
receiver gain, the gain control is locked for the remainder of
the packet.
RX_AGC_IN Interface
The signal level in the IF stage is monitored to determine
when to impose the 30dB gain reduction in the RF stage.
This maximizes the dynamic range of the receiver by
keeping the RF stages out of saturation at high signal levels.
When the IF circuit’s sensor output reaches 0.5V
HFA3863 comparator switches in the 30dB pad and also
adds 30dB of gain to the IF AGC amplifier. This
compensates the IF AGC and RSSI measures.
TX I/Q DAC Interface
The transmit section outputs balanced differential analog
signals from the transmit DACs to the HFA3783. These are
DC coupled and digitally filtered.
Test Port
The HFA3863 provides the capability to access a number of
internal signals and/or data through the Test port, pins TEST
7:0. The test port is programmable through configuration
register (CR 34). Any signal on the test port can also be read
from configuration register (CR50) via the serial control port.
Additionally, the transmit DACs can be configured to show
signals in the receiver via CR 14. This allows visibility to
analog like signals that would normally be very difficult to
capture.
DD
, the