STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 51

• Manufacturer Part Number: STG3005A2S
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

128-BIT 3D MULTIMEDIA ACCELERATOR
8.4
Table 15 shows the Video Port pin definition when
the RIVA128ZX is configured in ITU-R-656 Master
Mode. Before entering this mode, RIVA128ZX dis-
ables all Video Port devices so that the bus is tri-
stated. The RIVA128ZX will then enable the video
656 master device through the serial bus. In this
mode, the video device outputs the video data
continuously at the PIXCLK rate.
Table 15. 656 master mode pin definition
656 master mode timing specification
Figure 62. 656 Master Mode timing diagram
Table 16. ITU-R-656 Master Mode timing parameters
NOTE
Table 17. YUV (YCbCr) byte ordering
Symbol
MPCLK
MPAD[7:0]
MPFRAME#
MPDTACK#
MPSTOP#
1st byte
Cb[7:0]
t
t
t
U[7:0]
3
4
5
656 MASTER MODE
1 VACTIVE indicates that valid pixel data is being transmitted across the video port.
Normal Mode
VID[7:0] hold from PIXCLK high
VID[7:0] setup to PIXCLK high
PIXCLK cycle time
VID[7:0]
PIXCLK
2nd byte
Y0[7:0]
Y0[7:0]
PIXCLK
VID[7:0]
Not used
Not used
Not used
Parameter
656 Master Mode
3rd byte
Cr[7:0]
V[7:0]
t
4
t
3
t
4th byte
5
Y1[7:0]
Y1[7:0]
t
4
The 656 Master Mode assumes that VID[7:0] and
PIXCLK can be tri-stated when the slave is inac-
tive. If a slave cannot tri-state all its signals, an ex-
ternal tri-state buffer is needed.
Video data capture
Video Port pixel data is clocked into the port by the
external pixel clock and then passed to the
RIVA128ZX’s video capture FIFO.
Pixel data capture is controlled by the ITU-R-656
codes embedded in the data stream; each active
line beginning with SAV (start active video) and
ending with EAV (end active video).
In normal operation, when SAV = x00, capture of
video data begins, and when EAV = xx1, capture
of video data ends for that line. When VBI (Vertical
Blanking Interval) capture is active, these rules are
modified.
Min.
35
0
5
t
3
5th (next
dword)
Cb[7:0]
U[7:0]
Max.
t
4
6th byte
t
Y0[7:0]
Y0[7:0]
3
Unit
ns
ns
ns
RIVA128ZX
7th byte
Cr[7:0]
Notes
V[7:0]
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