STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 61

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STG3005A2S

Manufacturer Part Number
STG3005A2S
Description
128-BIT 3D MULTIMEDIA ACCELERATOR
Manufacturer
STMicroelectronics
Datasheet
128-BIT 3D MULTIMEDIA ACCELERATOR
11.6 TV OUTPUT SUPPORT
Reference clock options
The RIVA128ZX supports two synthesizer refer-
ence
14.31818MHz. The reference clock frequency is
determined by a crystal or reference clock con-
nected to the XTALIN and XTALOUT pins. Where
TV-out is supported, XTALOUT should be driven
by a 13.5MHz reference clock derived from an ex-
ternal NTSC/PAL clock source as illustrated in
Figure 67. The clock frequency should match the
power-on configuration setting described in Sec-
tion 10, page 55.
PAL/NTSC TV interface
The RIVA128ZX supports TV output through an
external Analog Devices AD722 PAL/NTSC RGB
encoder chip as shown in Figure 67. A MicroClock
Figure 67. TV output implementation
220
330
27pF
27pF
clock
13.50000MHz
5V
crystal
frequencies;
XTALIN
XTALOUT
X1/ICLK
X2
Clock Source
RIVA128ZX
NTSC/PAL
MK2715
VIDHSYNC
REFOUT
4XCLK
13.5MHz
G
R
B
33
33
and
75
MK2715 NTSC/PAL clock chip provides a com-
mon source for synchronization of the pixel and
subcarrier clocks. In TV output modes the
RIVA128ZX XTALOUT pin must be externally
driven from the MK2715 reference clock output,
with XTALIN tied to GND.
The MK2715 requires a number of external com-
ponents for proper operation. For crystal input a
parallel resonant 13.5000MHz crystal is recom-
mended, with a frequency tolerance of 50ppm or
better. Capacitors should be connected from X1
and X2 to GND as shown in Figure 67. Alternative-
ly a clock input (e.g. ClockCan) can be connected
to X1, leaving X2 disconnected. Further details are
given in the MK2715 datasheet [8].
RIN
GIN
BIN
HSYNC
FIN
RGB Encoder
AD722 TV
CVOUT
YOUT
COUT
220 F
220 F
220 F
RIVA128ZX
75
75
75
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