STG3005A2S STMicroelectronics, STG3005A2S Datasheet - Page 8

• Manufacturer Part Number: STG3005A2S
• Description: 128-BIT 3D MULTIMEDIA ACCELERATOR
• Manufacturer: STMicroelectronics

RIVA128ZX
2.5
2.6
2.7
2.8
8/85
Signal
Signal
Signal
Signal
RED,
GREEN,
BLUE
COMP
RSET
VREF
XTALIN
XTALOUT
DACVDD
PLLVDD
VDD
GND
MPCLAMP
HOSTVDD
HOSTCLAMP
ROMCS#
SDA
SCL
VIDVSYNC
VIDHSYNC
DEVICE ENABLE SIGNALS
DISPLAY INTERFACE
VIDEO DAC AND PLL ANALOG SIGNALS
POWER SUPPLY
I/O
I/O
I/O
I/O
I/O
I/O
O
O
P
P
P
P
P
P
P
O
O
O
-
-
-
I
Description
Description
Description
Description
RGB display monitor outputs. These are software configur able to drive either a doubly ter-
minated or singly terminated 75 load.
External compensation capacitor for the video DACs. This pin should be connected to
DACVDD via the compensation capacitor, see Figure 66, page 60.
A precision resistor placed between this pin and GND sets the full-scale video DAC cur-
rent, see Figure 66, page 60.
A capacitor should be placed between this pin and GND as shown in Figure 66, page 60.
A series resonant crystal is connected between these two points to provide the reference
clock for the internal MCLK and VCLK clock synthesizers, see Figure 66 and Table 20,
page 60. Alternately, an external LVTTL clock oscillator output may be driven into XTA-
LOUT, connecting XTALIN to GND. For designs supporting TV-out, XTALOUT should be
driven by a reference clock as described in Section 11.6, page 61.
Analog power supply for the video DACs.
Analog power supply for all clock synthesizers.
Digital power supply.
Ground.
MPCLAMP is connected to +5V to protect the 3.3V RIVA128ZX from external devices
which will potentially drive 5V signal levels onto the Video Port input pins.
HOSTVDD is connected to the Vddq 3.3 pins on the AGP connector. This is the supply
voltage for the I/O buffers and is isolated from the core VDD. On AGP designs these pins
are also connected to the HOSTCLAMP pins. On PCI designs they are connected to the
3.3V supply.
HOSTCLAMP is the supply signalling rail protection for the host interface. In AGP designs
these signals are connected to Vddq 3.3. For PCI designs they are connected to the I/O
power pins (V
Enables reads from an external 64Kx 8 or 32Kx8 ROM or Flash ROM. This signal is used
in conjunction with framebuffer data lines as described above in Section 2.3.
Used for DDC2B+ monitor communication and interface to video decoder devices.
Used for DDC2B+ monitor communication and interface to video decoder devices.
Vertical sync supplied to the display monitor. No buffering is required. In TV mode this sig-
nal supplies composite sync to an external PAL/NTSC encoder.
Horizontal sync supplied to the display monitor. No buffering is required.
(I/O)
).
128-BIT 3D MULTIMEDIA ACCELERATOR