MBM29PDS322TE Fujitsu Microelectronics, Inc., MBM29PDS322TE Datasheet - Page 19

• Manufacturer Part Number: MBM29PDS322TE
• Description: Flash Memory 32m 2m X 16 Bit Page Dual Operation
• Manufacturer: Fujitsu Microelectronics, Inc.

Simultaneous Operation
*: An erase operation may also be suspended to read from or program to a sector not being erased.
Read Mode
Page Mode Read
FUNCTIONAL DESCRIPTION
The device has feature, which is capable of reading data from one bank of memory while a program or erase
operation is in progress in the other bank of memory (simultaneous operation), in addition to the conventional
features (read, program, erase, erase-suspend read, and erase-suspend program). The bank selection can be
selected by bank address (A
The device has two banks which contain
The simultaneous operation can not execute multi-function mode in the same bank. Table 8 shows the possible
combinations for simultaneous operation. (Refer to Figure 12 Back-to-Back Read/Write Timing Diagram.)
The device has two control functions which must be satisfied in order to obtain data at the outputs. CE is the
power control and should be used for a device selection. OE is the output control and should be used as the
gate data to the output pins if a device is selected.
Address access time (t
time (t
access time (t
have been stable for at least t
it is necessary to input hardware reset or to change CE pin from “H” or “L”.
The device is capable of fast Page mode read operation. This mode provides faster read access speed for
random locations within a page. The Page size of the device is 4 words, within the appropriate Page being
selected by the higher address bits A
operation with the microprocessor supplying the specific word location.
The random or initial page access is equal to t
specified by the microprocessor fall within that Page) is equivalent to t
and OE is the output control and should be used to gate data to the output pins if the device is selected. Fast
Page mode accesses are obtained by keeping A
word, within that page. See Figure 5.4 for timing specifications.
Bank 1 (4 KW
Case
CE
1
2
3
4
5
6
7
) is the delay from stable addresses and stable CE to valid data at the output pins. The output enable
OE
) is the delay from the falling edge of OE to valid data at the output pins. (Assuming the addresses
eight sectors, 32 KW
ACC
) is equal to delay from stable addresses to valid output data. The chip enable access
20
ACC
to A
-t
OE
Autoselect mode
15
Bank 1 Status
Program mode
Erase mode *
20
) with zero latency.
time.) When reading out data without changing addresses after power-up,
Read mode
Read mode
Read mode
Read mode
to A
Table 8 Simultaneous Operation
2
seven sectors) and Bank 2 (32 KW
and the LSB bits A
ACC
20
and subsequent Page read access (as long as the locations
to A
MBM29PDS322TE/BE
2
constant and changing A
1
and A
0
within that page. This is an asynchronous
PACC
. Here again, CE selects the device
Autoselect mode
Bank 2 Status
Program mode
fifty-six sectors).
Erase mode *
1
Read mode
Read mode
Read mode
Read mode
and A
0
to select the specific
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