MBM29PDS322TE Fujitsu Microelectronics, Inc., MBM29PDS322TE Datasheet - Page 9

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MBM29PDS322TE

Manufacturer Part Number
MBM29PDS322TE
Description
Flash Memory 32m 2m X 16 Bit Page Dual Operation
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
*1: This command is valid while Fast Mode.
*2: This command is valid while RESET = V
*3: This command is valid while Hi-ROM mode.
*4: The data “00h” is also acceptable.
Note 1.Address bits A
Read/Reset Word
Read/Reset Word
Auto
select
Program
Chip Erase
Sector
Erase
Erase Suspend
Erase Resume
Set to
Fast Mode
Fast
Program *
Reset from
Fast Mode *
Extended
Sector Group
Protection *
Query
Hi-ROM
Entry
Hi-ROM
Program *
Hi-ROM
Erase *
Hi-ROM
Exit *
Command
Sequence
3
2.Bus operations are defined in Table 8.
3.RA =
3
Address (SA), and Bank Address (BA).
PA =
1
3
2
1
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Word
Address of the memory location to be programmed
Address of the memory location to be read
Addresses are latched on the falling edge of the write pulse.
Cycles
Req’d
Write
Bus
20
1
3
3
4
6
6
1
1
3
2
2
4
1
3
4
6
4
to A
12
Write Cycle
Table 4: MBM29PDS322TE/BE Command Definitions
XXXh F0h
XXXh A0h
XXXh 60h
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
(BA)
= X = “H” or “L” for all address commands except or Program Address (PA), Sector
First Bus
55h
BA
BA
BA
B0h
30h
90h XXXh
98h
ID
Second Bus
.
Write Cycle
SPA
PA
F0h
60h
PD
*
MBM29PDS322TE/BE
4
Write Cycle
(HRBA)
555h
555h
555h
555h
555h
555h
555h
555h
555h
555h
Third Bus
(BA)
SPA
A0h
A0h
F0h
90h
80h
80h
20h
40h
88h
80h
90h XXXh 00h
(HRA)
Fourth Bus
Read/Write
555h AAh 2AAh 55h
555h AAh 2AAh 55h
555h AAh 2AAh 55h
SPA
RA
PA
PA
Cycle
RD
PD
SD
PD
Write Cycle
Fifth Bus
Write Cycle
555h
HRA
Sixth Bus
SA
10/11
10h
30h
30h
9

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