MBM29PDS322TE Fujitsu Microelectronics, Inc., MBM29PDS322TE Datasheet - Page 23

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MBM29PDS322TE

Manufacturer Part Number
MBM29PDS322TE
Description
Flash Memory 32m 2m X 16 Bit Page Dual Operation
Manufacturer
Fujitsu Microelectronics, Inc.
Datasheet
Read/Reset Command
Autoselect Command
COMMAND DEFINITIONS
The device operations are selected by writing specific address and data sequences into the command register.
Some commands require Bank Address (BA) input. When command sequences are inputted to bank being read,
the commands have priority over reading. Table 4 defines the valid register command sequences. Note that the
Erase Suspend (B0h) and Erase Resume (30h) commands are valid only while the Sector Erase operation is
in progress. Moreover, both Read/Reset commands are functionally equivalent, resetting the device to the read
mode. Please note that commands are always written at DQ
In order to return from Autoselect mode or Exceeded Timing Limits (DQ
Reset operation is initiated by writing the Read/Reset command sequence into the command register. Micro-
processor read cycles retrieve array data from the memory. The device remains enabled for reads until the
command register contents are altered.
The device will automatically power-up in the Read/Reset state. In this case, a command sequence is not required
to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no
spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Character-
istics and Waveforms for the specific timing parameters.
Flash memories are intended for use in applications where the local CPU alters memory contents. As such,
manufacture and device codes must be accessible while the device resides in the target system. PROM pro-
grammers typically access the signature codes by raising A
onto the address lines is not generally desired system design practice.
The device contains an Autoselect command operation to supplement traditional PROM programming method-
ology. The operation is initiated by writing the Autoselect command sequence into the command register.
The Autoselect command sequence is initiated by firstly writing two unlock cycles. This is followed by a third
write cycle that contains the bank address (BA) and the Autoselect command. Then the manufacture and device
codes can be read from the bank, and actual data of memory cell can be read from the another bank.
Following the command write, a read cycle from address (BA)00h retrieves the manufacture code of 04h. A read
cycle at address (BA)01h returns 7Eh to indicate that this device uses extended device code. The successive
read cycle from (BA)0Eh to (BA)0Fh returns this extended device code for this device. (See Tables 5.1 to 5.4.)
The sector state (protection or unprotection) will be informed by address (BA)02h. Scanning the sector group
addresses (A
logical “1” at device output DQ
by verify sector group protection on the protected sector. (See Table 3.)
The manufacture and device codes can be allowed to read from selected bank. To read the manufacture and
device codes and sector protection status from non-selected bank, it is necessary to write Read/Reset command
sequence into the register and then Autoselect command should be written into the bank to be read.
If the software (program code) for Autoselect command is stored into the Flash memory, the device and manu-
facture codes should be read from the other bank which doesn’t contain the software.
To terminate the operation, it is necessary to write the Read/Reset command sequence into the register. To
execute the Autoselect command during the operation, writing Read/Reset command sequence must precede
the Autoselect command.
20
, A
19
, A
18
, A
17
, A
0
16
for a protected sector group. The programming verification should be performed
, A
15
, A
14
, A
13
, and A
12
MBM29PDS322TE/BE
) while (A
9
to a high voltage. However, multiplexing high voltage
7
to DQ
6
, A
3
0
, A
and DQ
2
, A
5
= 1) to Read/Reset mode, the Read/
1
, A
15
0
) = (0, 0, 0, 1, 0) will produce a
to DQ
8
bits are ignored.
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