XR17C158 Exar Corporation, XR17C158 Datasheet - Page 10

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

PRELIMINARY
N
RWR=Read/Write from AD[31:0]. RO= Read Only.
RWC=Read/Write-Clear.
The device configuration registers and a special way
to access each of the UART’s transmit and receive
data FIFOs are accessible directly from the PCI data
bus. This provides easy programming of general op-
erating parameters to the 158 UART and for monitor-
ing the status of various functions. The registers oc-
cupy 4K of PCI bus memory address space. These
addresses are offset onto the basic memory address,
a value loaded into the Memory Base Address Regis-
ter (BAR) in the PCI local bus configuration register
set. These registers control or report on all 8 channel
UARTs funtions that include interrupt control and sta-
tus, 16-bit general purpose timer control and status,
multipurpose inputs/outputs control and status, sleep
mode control, soft-reset control, and device indentifi-
cation and revision, and others.
1.2 D
OTE
A
DDRESS
0x2C
0x3C
0x28
0x30
0x34
0x38
: RWR
EVICE
1
=Read/Write from external EEPROM.
31:0
31:16
15:0
31:0
31:0
31:0
31:24
23:16
15:8
7:0
C
B
ONFIGURATION
ITS
RWR
RWR
RWR
T
RO
RO
RO
RO
RO
RO
RO
T
YPE
ABLE
1
1
R
EGISTER
1: PCI L
Reserved
Subsystem ID (write from external EEPROM by customer)
Subsystem Vendor ID (write from external EEPROM by cus-
tomer)
Expansion ROM Base Address (Unimplemented)
Reserved (returns zeros)
Reserved (returns zeros)
Unimplemented MAXLAT
Unimplemented MINGNT
Interrupt Pin, use INTA#.
Interrupt Line.
OCAL
S
ET
B
US
C
ONFIGURATION
10
D
The registers set is mapped into 8 address blocks
where each UART channel occupies 512 bytes mem-
ory space for its own 16550 compatible configuration
registers. The device configuration and control regis-
ters are embedded inside the UART channel zero’s
address space between 0x0080 to 0x0093. All these
registers can be accessed in 8, 16, 24 or 32 bit width
depending on the starting address given by the host
at beginning of the bus cycle. Transmit and receive
data may be loaded or unloaded in 8, 16, 24 or 32 bit
format to the register’s address. Every time a read or
write operation is made to the transmit or receive reg-
ister, its FIFO data pointer is automatically bumped to
the next sequential data location either in byte, word
or dword. One special case applies to the receive da-
ta unloading when reading the receive data together
with its LSR register content. The host must read
them in 16 or 32 bits format in order to maintain integ-
rity of the data byte with its associated error flags.
ESCRIPTION
S
PCI BUS OCTAL UART
PACE
R
EGISTERS
R
0x00000000
0x00000000
0x00000000
0x00000000
XR17C158
ESET
0x0000
0x0000
(
0xXX
0x00
0x00
0x01
HEX
REV. 1.0.0
V
ALUE
)