XR17C158 Exar Corporation, XR17C158 Datasheet - Page 21

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

XR17C158
REV. 1.0.0
The THR and RHR register address for channel 0 to
channel 7 is shown in
RHR for each channel 0 to 7 are located sequentially
at address 0x0000, 0x0200, 0x0400, 0x0600,
There are 8 UARTs [channel 7:0] in the 158. Each
has its own 64-byte of transmit and receive FIFO, a
set of 16550 compatible control and status registers,
and a baud rate generator for individual channel data
3.2 FIFO DATA LOADING AND UNLOADING
4.0 UART
Data Bit-31
PCI Bus
B7 B6 B5 B4 B3 B2 B1 B0
THROUGH THE UART CHANNEL REGIS-
TERS, THR AND RHR IN 8-BIT FORMAT.
Receive Data Byte n+1
T
ABLE
PCI BUS OCTAL UART
CH0 0x000 Read RHR
CH2 0x400 Read RHR
CH3 0x600 Write THR
CH3 0x600 Read RHR
CH4 0x800 Read RHR
CH5 0xA00 Write THR
CH6 0xC00 Read RHR
CH0 0x000 Write THR
CH1 0x200 Write THR
CH1 0x200 Read RHR
CH2 0x400 Write THR
CH4 0x800 Write THR
CH5 0xA00 Read RHR
CH7 0xE00 Read RHR
CH6 0xC00 Write THR
8: T
Channel 0 to 7 Receive Data with Line Status Register in a 32-bit alignment through the Configuration
CH7 0xE00 Write THR
RANSMIT AND
THR and RHR Address Locations For CH0 to CH7 (16C550 Compatible)
Register Address 0x0180, 0x0380, 0x0580, 0x0780, 0x0980, 0x0B80, 0x0D80 and 0x0F80
Table 8
B7 B6 B5 B4 B3 B2 B1 B0
below. The THR and
Line Status Register n+1
R
ECEIVE
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
D
ATA
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
Bit-6
R
EGISTER IN
21
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
Bit-5
B7 B6 B5 B4 B3 B2 B1 B0
0x0800, 0x0A000, 0x0C00 and 0x0E00. Transmit da-
ta byte is loaded to the THR when writting to that ad-
dress and receive data is unloaded from the RHR
register when reading that address. Both THR and
RHR registers are 16C550 comptible in 8-bit format,
so each bus operation can only write or read in bytes.
rate setting. Eight additional registers per UART were
added for the EXAR enhanced features.
Each UART has its own Baud Rate Generator (BRG)
with a prescaler for the transmiter and receiver. The
prescaler is controlled by a software bit in the MCR
4.1 P
Receive Data Byte n+0
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
Bit-4
B
ROGRAMMABLE
YTE FORMAT
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
, 16C550
B
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
AUD
B7 B6 B5 B4 B3 B2 B1 B0
Line Status Register n+0
R
THRRHR1
COMPATIBLE
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
Bit-0
PRELIMINARY
ATE
G
ENERATOR
Data Bit-0
PCI Bus