XR17C158 Exar Corporation, XR17C158 Datasheet - Page 14

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

PRELIMINARY
The second scheme provides detail about the source
of the interrupts for each UART channel. All the inter-
rupts are encoded into a 3-bit code. This 3-bit code
represents 7 interrupts corresponding to individual
UART’s transmitter, receiver, line status, modem port
status. INT1, INT2 and INT3 registers provide the 24-
bit interrupt status for all 8 channels. Bits 8,9 and 10
representing
31representing channel 7 respectively. All 8 channel
interrupts status are available with a single DWORD
read operation. This feature allows the host quickly
vectors and serves the interrupts, reducing service in-
terval, hence, reduce host bandwidth requirement.
GLOBAL INTERRUPT REGISTER (DWORD)
fault 0x00-00-00-00]
All bits start up zero. A special interrupt condition is
generated by the 158 upon awakening from sleep af-
ter all 8 channels were put to sleep mode earlier.
Figure 4
make up.
INT0 [7:0] Channel Interrupt Indicator.
Each bit gives an indication of the channel that has
requested for service. Bit-0 represents channel 0 and
F
INT3 [31:24] INT2 [23:16] INT1 [15:87]
IGURE
N+2
Bit
Channel-7
N+1
Bit
4. T
shows the 4-byte interrupt register and its
Bit
N
HE
INT3 Register
channel
G
N+2
Bit
LOBAL
Channel-6
N+1
Bit
I
Bit
N
NTERRUPT
0
N+2
Bit
and
Channel-5
N+1
Bit
R
bits
EGISTER
Bit
N
N+2
Bit
29,30
INT0 [7:0]
Channel-4
, INT0, INT1, INT2
N+1
INT0, INT1, INT2 and INT3
Bit
Interrupt Registers,
INT2 Register
[de-
and
Bit
N
N+2
14
Bit
Channel-3
The INT0 register provides individual status for
each channel
bit-7 indicates channel 7. Logic one indicates the
channel N [7:0] has called for service. The interrupt
bit clears after reading the appropiate register of the
interrupting channel register, see Interrupt Clearing
section.
INT3, INT2 and INT1 [32:8] Twenty four bit encoded
interrupt indicator. Each channel’s interrupt is encod-
ed into 3 bits for receive, transmit, and status. Bit
[10:8] represent channel 0 and go up to channel 7
with bits [31:29]. The 3 bit encoding and their priority
order are shown below in Table 5. The Timer and
MPIO interrupts are for the device and therefore they
exist within channel 0 space and not in other channel
interrupt.
.
N+1
Bit
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Ch-7
Bit
N
AND
Individual UART Channel Interrupt Status
N+2
Ch-6
Bit
PCI BUS OCTAL UART
INT3
Channel-2
N+1
Ch-7
Bit-7
Bit
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Ch-6
Bit-6
Bit
N
INT0 Register
Ch-5
Bit-5
N+2
Bit
Channel-1
INT0 Register
Ch-4
Bit-4
N+1
INT1 Register
Bit
Ch-3
Bit-3
Bit
N
Ch-2 Ch-1 Ch-0
N+2
Bit-2
Bit
Channel-0
XR17C158
N+1
Bit-1
Bit
Bit-0
REV. 1.0.0
Bit
N