XR17C158 Exar Corporation, XR17C158 Datasheet - Page 34

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

PRELIMINARY
FCR BIT-0: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO. (de-
fault).
Logic 1 = Enable the transmit and receive FIFOs.
This bit must be set to logic 1 when other FCR bits
are written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No receive FIFO reset. (default)
Logic 1 = Reset the receive FIFO pointers and FIFO
level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is active.
Logic 0 = No transmit FIFO reset. (default)
Logic 1 = Reset the transmit FIFO pointers and FIFO
level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after
resetting the FIFO.
FCTR
B
IT
0
0
1
1
-7
FCTR
B
IT
0
1
0
1
-6
B
FCR
IT
X
0
0
1
1
0
0
1
1
0
0
1
1
T
-7
ABLE
B
FCR
13: T
IT
0
1
0
1
0
1
0
1
0
1
0
1
X
-6
RANSMIT AND
B
FCR
IT
X
0
0
0
1
1
0
0
1
1
-5
BIT
FCR
X
0
0
1
0
1
0
1
0
1
-4
R
ECEIVE
T
Programmable Programmable Table-D. 16C850, 16c2850,
RIGGER
1 (default)
R
ECEIVE
34
14
16
24
28
16
56
60
FIFO T
4
8
8
8
FCR[3]: DMA Mode Select
This bit has no effect since TXRDY and RXRDY pins
are not available in this device. It is provided for lega-
cy software.
Logic 0 = Set DMA to mode 0. (default)
Logic 1 = Set DMA to mode 1.
FCR[5:4]: Transmit FIFO Trigger Select
(logic 0 = default, TX trigger level = one)
The FCTR Bits 6-7 are associated with these 2 bits
by selecting one of the four tables. The 4 user select-
able trigger levels in 4 tables are supported for com-
patibility reasons. These 2 bits set the trigger level for
the transmit FIFO interrupt. The UART will issue a
transmit interrupt when the number of characters in
the FIFO falls below the selected trigger level, or
when it gets empty in case that the FIFO did not get
filled over the trigger level on last re-load.
below shows the selections.
FCR[7:6]: Receive FIFO Triggeer Select
(logic 0 = default, RX trigger level =1)
The FCTR Bits 6-7 are associated with these 2 bits.
These 2 bits are used to set the trigger level for the
receiver FIFO interrupt.
selections.
L
EVEL
RIGGER
T
RIGGER
1 (default)
T
PCI BUS OCTAL UART
RANSMIT
16
24
30
16
32
56
L
8
8
EVEL
L
EVEL
S
ELECTION
Table-A. 16C550, 16C2550,
16C2552, 16C554, 16C580
compatible.
Table-B. 16C650A compatible.
Table-C. 16C654 compatible.
16C2852, 16C854, 16C864,
16C872 compatible.
Table 13
C
OMPATIBILITY
shows the complete
XR17C158
REV. 1.0.0
Table 13