XR17C158 Exar Corporation, XR17C158 Datasheet - Page 41

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

XR17C158
REV. 1.0.0
• Logic 0 = Automatic CTS/DSR flow control is dis-
• Logic 1 = Enable Automatic CTS/DSR flow control.
TFCNT[7:0] : Transmit FIFO Level Counter, read-
only
Transmit FIFO level byte count from 0x00 (zero) to
0x40 (64). This 8-bit register gives an indication of the
number of characters in the transmit FIFO. The
FIFO level Byte count register is read only. The user
can take advantage of the FIFO level byte counter for
faster data loading to the transmit FIFO., which re-
duces CPU bandwidth requirements.
TXTRG [7:0]: Transmit FIFO Trigger Level, write
only.
An 8-bit value written to this register sets the TX FIFO
trigger level from 0x00 (zero) to 0x40 (64). The TX
FIFO trigger level generates an interrupt whenever
the data level in the transmit FIFO falls below this
preset trigger level.
RFCNT[7:0]: Receive FIFO Level Counter, read
only
Receive FIFO level byte count from 0x00 (zero) to
0x40 (64). It gives an indication of the number of
characters in the receive FIFO. The FIFO level byte
count register is read only. The user can take advan-
tage of the FIFO level byte counter for faster data un-
loading from the receiver FIFO, which reduces CPU
bandwidth requirements.
RXTRG[7:0]: Receive FIFO Trigger Level, write
only
An 8-bit value written to this register, sets the RX
FIFO trigger level from 0x00 (zero) to 0x40 (64). The
RX FIFO trigger level generates an interrupt whenev-
er the receive FIFO level rises to this preset trigger
level.
abled. (default)
Transmission stops when CTS/DSR# pin de-
asserts to logic 1. Transmission resumes when
CTS/DRS# pin returns to a logic 0. The selection
for CTS# or DSR# is through MCR bit-2.
PCI BUS OCTAL UART
41
I/O SIGNALS
DTR#[ch-7:0]
REGISTERS
RTS#[ch-7:0]
IRTX[ch-7:0]
TX[ch-7:0]
XCHAR
TFCNT
TFTRG
RFCNT
RFTRG
XOFF1
XOFF2
FCTR
XON1
XON2
EECK
EECS
T
MCR
MSR
EEDI
DLM
RHR
THR
FCR
LCR
SPR
EFR
DLL
LSR
IER
ISR
ABLE
18: UART RESET CONDITIONS
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
Bits 3-0 = logic 0
Bits 7-4 = logic levels of the inputs
Bits 7-0 = 0xFF
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Logic 1
Logic 0
Logic 1
Logic 1
Logic 0
Logic 0
Logic 0
RESET STATE
RESET STATE
PRELIMINARY