XR17C158 Exar Corporation, XR17C158 Datasheet - Page 39

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

XR17C158
REV. 1.0.0
FCTR[4]: Infrared RX Input Logic Select
0 = Select RX input as active high encoded IrDA da-
ta, normal, (default).
1 = Select RX input as active low encoded IrDA data,
inverted.
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable.
• 0 = Standard ST16C550 mode. Transmitter gener-
• 1 = Enable Auto RS485 half duplex direction con-
FCTR[7:6]: TX and RX FIFO Trigger Table Select
These 2 bits select the transmit and receive FIFO trig-
ger level table A, B, C or D. When table A, B, or C is
ates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register
(TSR) may still be shifting data bit out.
trol. RTS# output changes its logic level from 1 to 0
when finished sending the last stop bit of the last
character out of the TSR register. It changes back
to logic level 1 from 0 when a data byte is loaded
into the THR or transmit FIFO. The change to logic
1 occurs prior sending the start-bit. It also changes
the transmitter interrupt from transmit holding to
transmit shift register (TSR) empty.
T
ABLE
PCI BUS OCTAL UART
FCTR B
16: 16 S
0
0
1
1
1
1
1
1
1
1
IT
-3 FCTR B
ELECTABLE
1
1
1
1
1
1
0
0
0
0
IT
-2 FCTR B
H
YSTERESIS
1
1
0
0
1
1
0
0
1
1
IT
-1 FCTR B
L
EVELS
39
selected the auto RTS flow control trigger level is set
to "next FIFO trigger level" for compatibility to
ST16C550 and ST16C650 series. RTS/DTR# trig-
gers on the next level of the RX FIFO trigger level, in
another word, one FIFO level above and one FIFO
level below. See in
with FCR bit 4-5 and FCTR bit 6-7, i.e. if Table C is
used on the receiver with RX FIFO trigger level set to
56 bytes, RTS/DTR# output will de-asserts at 60 and
re-asserts at 16.
Enhanced Feature Register (EFR)
Enhanced features are enabled or disabled using this
register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
Table 17). When the Xon1 and Xon2 and Xoff1 and
Xoff2 modes are selected, the double 8-bit words are
concatenated into two sequential characters. Cau-
tion: note that whenever changing the TX or RX flow
control bits, always reset all bits back to logic 0 (dis-
able) before programming a new setting.
EFR BIT 0-3: Software Flow Control Select
Combinations of software flow control can be select-
ed by programming these bits.
0
1
0
1
0
1
0
1
0
1
W
IT
HEN
-0
T
RIGGER
RTS/DTR H
(
CHARACTERS
T
ABLE
+/- 24
+/- 32
+/- 12
+/- 20
+/- 28
+/- 36
+/- 40
+/- 44
+/- 48
+/- 52
Table 13
YSTERESIS
-D
IS
)
S
for complete selection
PRELIMINARY
ELECTED