XR17C158 Exar Corporation, XR17C158 Datasheet - Page 30

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

PRELIMINARY
The receiver section contains an 8-bit Receive Shift
Register (RSR) and Receive Holding Register (RHR).
The RSR uses the 16X or 8X clock for timing. It veri-
fies and validates every bit on the incoming character
in the middle of each data bit. On the falling edge of a
start or false start bit, an internal receiver counter
starts counting at the 16X or 8X clock rate. After 8 or
4 clocks the start bit period should be at the center of
the start bit. At this time the start bit is sampled and if
it is still a logic 0 it is validated. Evaluating the start bit
in this manner prevents the receiver from assembling
a false character. The rest of the data bits and stop
bits are sampled and validated in this same manner
to prevent false framing. If there were any error(s),
F
4.7 R
IGURE
ECEIVER
13. T
(8XMODE Register)
Auto Software Flow Control
(Xoff1/2 and Xon1/2 Reg.
Auto CTS Flow Control (CTS# pin)
Flow Control Characters
16X or 8X Clock
RANSMIITTER
O
Data Byte
Transmit
PERATION IN
FIFO
Transmit Data Shift Register
AND
F
(64-Byte)
Transmit
LOW
FIFO
(TSR)
30
they are reported in the LSR register bits 1- 4. Upon
unloading the receive data byte from RHR, the re-
ceive FIFO pointer is bumped and the error flags are
immediately updated to reflect the status of the data
byte in RHR register. RHR can generate a receive da-
ta ready interrupt upon receiving a character or delay
until it reaches the FIFO trigger level. Furthemore,
data delivery to the host is guaranteed by a receive
data ready time-out function when receive data does
not reach the receive FIFO trigger level. This time-out
delay is 4 word lengths as defined by LCR[1,0] plus
12 bits time. The RHR interrupt is enabled by IER bit-
0
C
4.7.1
ONTROL
Receiver Operation in non-FIFO Mode
PCI BUS OCTAL UART
M
ODE
THR Interrupt (ISR bit-1) falls
when becomes empty. FIFO
below Programmed Trigger
is Enabled by FCR bit-0=1
Level (TXTRG) and then
TXFIFO1
XR17C158
REV. 1.0.0