XR17C158 Exar Corporation, XR17C158 Datasheet - Page 20

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

PRELIMINARY
Each Channel Normal Transmit Data FIFO Address
for Channel 0 to 7 are at 0x0100, 0x0300, 0x0500,
0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00.
Each Channel Special Receive FIFO Data Address
for channel 0 to 7 are at 0x0180 0x-380, 0x0580,
0x0780, 0x0980, 0x0B80, 0x0D80 and 0x0F80. The
Data Bit-31
WITH N
Data Bit-31
PCI Bus
WITH LSR
Read n+0 to n+3
Read n+4 to n+7
Write n+0 to n+3
Write n+4 to n+7
Read n+0 to n+1
Read n+2 to n+3
R
PCI Bus
W
R
B7 B6 B5 B4 B3 B2 B1 B0
EAD
EAD
B7 B6 B5 B4 B3 B2 B1 B0
RITE
Transmit Data Byte n+3
Etc.
Etc.
RX FIFO,
RX FIFO,
Etc
Receive Data Byte n+3
O
TX FIFO
E
E
RRORS
RRORS
Channel 0 to 7 Transmit Data in 32-bit alignment through the Configuration Register Address
Channel 0 to 7 ReceiveData in 32-bit alignment through the Configuration Register Address
FIFO Data n+3
FIFO Data n+7
FIFO Data n+3
FIFO Data n+7
FIFO Data n+1
FIFO Data n+3
B
B
B
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
0x0100, 0x0300, 0x0500, 0x0700, 0x0900, 0x0B00, 0x0D00 and 0x0F00
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
YTE
YTE
YTE
Transmit Data Byte n+2
Receive Data Byte n+2
3
3
3
FIFO Data n+2
FIFO Data n+6
FIFO Data n+2
FIFO Data n+6
LSR n+1
LSR n+3
B
B
B
YTE
YTE
YTE
20
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Status and Data bytes must be read in 16 or 32 bits
format to maintain data integrity.
2
2
2
Transmit Data Byte n+1
Receive Data Byte n+1
PCI BUS OCTAL UART
FIFO Data n+1
FIFO Data n+5
FIFO Data n+1
FIFO Data n+5
FIFO Data n+0
FIFO Data n+2
B
B
B
YTE
YTE
YTE
1
1
1
B7 B6 B5 B4 B3 B2 B1 B0
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+0
Transmit Data Byte n+0
FIFO Data n+0
FIFO Data n+4
FIFO Data n+0
FIFO Data n+4
LSR n+0
LSR n+2
XR17C158
B
B
B
YTE
YTE
YTE
Data Bit-0
REV. 1.0.0
PCI Bus
Data Bit-0
0
0
0
PCI Bus