XR17C158 Exar Corporation, XR17C158 Datasheet - Page 19

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

XR17C158
REV. 1.0.0
MPIOINV [7:0] (default 0x00)
Input inversion control. A logic 0 (default) does not
invert the input pin logic. A logic 1 inverts the input
logic level.
MPIOSEL [7:0] (default 0xFF)
Multipurpose input/output pin select.
defines the functions of the pins. A logic 1 (default)
defines the pin for input and a logic "0" for output.
The 158 includes an on-chip oscillator (XTAL1 and
XTAL2). The crystal oscillator provides the system
clock to the Baud Rate Generators (BRG) in each of
the 8 UARTs, the 16-bit general purpose timer/
counter and internal logics. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin
being the output.
Generator in the UART section for programming de-
tails.
The on-chip oscillator is designed to use an industry
standard microprocessor crystal (parallel resonant
with 10-22 pF capacitance load, 100ppm) connected
externally between the XTAL1 and XTAL2 pins (see
Figure
nected to the XTAL1 pin to clock the internal 8 baud
rate generators for standard or custom rates. Typical-
ly, the oscillator connections are shown in Figure 7.
For further reading on oscillator circuit please see ap-
plication note DAN108 on EXAR’s web site.
2.0 CRYSTAL OSCILLATOR / BUFFER
MPIO7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
7). Alternatively, an external clock can be con-
MPIO7
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Multipurpose Input Signal Inversion Enable
MPIO6
Multipurpose Input/Output Selection
MPIO6
MPIO6
Multipurpose Output 3-state Enable
PCI BUS OCTAL UART
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOSEL Register
MPIOINV Register
MPIO3T Register
See Programmable Baud Rate
This register
19
F
There are two methods to load transmit data and un-
load receive data from each UART channel. First,
there is a transmit data register and receive data reg-
ister for each UART channel in the device configura-
tion register set to ease programming. These regis-
ters support 8,
32-bit format, it increases the data transfer rate on
the PCI bus. Additionally, a special register location
provides receive data byte with its associated error
flags. This is a 16-bit or 32-bit read operation where
the Line Status Register (LSR) content in the UART
channel register is paired along with the data byte.
This operation further facilitates data unloading with
the error flags without having to read the LSR register
separately. Furthermore, the XR17C158 supports
PCI burst mode for read/write operation of up to 64
bytes of data.
The second method is through each UART channel’s
transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are
16550 compatible so their access is limited to 8-bit
format. The software driver must separately read the
LSR content for the associated error flags before
reading the data byte.
The transmit and receive data registers are defined
for channel 0 to channel 7 with each channel having
it’s own address as shown in
ing and unloading. The following paragraphs illustrate
the receive and transmit data registers in more detait.
Each Channel Normal Receive Data FIFO Address
for channels 0 to 7 are at 0x0100, 0x0300, 0x0500,
0x0700, 0x0900, 0x0B000, 0x0D00 and 0x0F00.
3.0 TRANSMIT AND RECEIVE DATA
3.1 FIFO DATA LOADING AND UNLOADING
IGURE
THROUGH THE DEVICE CONFIGURATION
REGISTERS IN 32-BIT FORMAT.
7. T
YPICAL OSCILLATOR CONNECTIONS
22-47pF
XTAL1
16,
C1
R=300K to 400K
24 and 32 bits wide format. In the
14.7456
MHz
Table 2
PRELIMINARY
22-47pF
XTAL2
C2
for faster load-