XR17C158 Exar Corporation, XR17C158 Datasheet - Page 15

• Manufacturer Part Number: XR17C158
• Description: Eight-channel Pci-based (UART)
• Manufacturer: Exar Corporation

XR17C158
REV. 1.0.0
A 16-bit down-count timer for general purpose timer
or counter. Its clock source may be selected from in-
ternal crystal oscillator or externally on pin TMRCK.
The timer can be set to be a single-shot for a one-
time event or re-triggerable for continue interval. An
RXRDY and RXRDY Time-out is clear by reading data in the RX FIFO until it falls below the trigger level.
RX Line Status interrupt clears after reading the LSR register.
TXRDY interrupt clears after reading ISR register that is in the UART channel register set.
Modem Status Register interrupt clears after reading MSR register that is in the UART channel register set.
RTS/CTS or DTR/DSR delta interrupt clears after reading MSR register that is in the UART channel register set.
Xoff/Xon delta and special character detect interrupt clears after reading the ISR register that is in the UART channel reg-
ister set.
TIMER Time-out interrupt clears after reading the TIMERCNTL register that is in the Device Configuration register set.
MPIO interrupt clears after reading the MPIOLVL register that is in the Device Configuration register set.
[TIMERMSB, TIMELSB, TIMER, TIMECNTL]
(
P
DEFAULT
1.2.2 General Purpose 16-bit Timer/Counter.
RIORITY
x
1
2
3
4
5
6
7
F
IGURE
0
B
X
TIMERCNTL [3]
XX-XX-00-00)
TIMERCNTL [1]
TIMERCNTL [2]
TIMERCNTL [0]
TIMERCNTL [4]
IT
5. T
TIMERMSB and TIMERLSB
OSC. CLOCK
PCI BUS OCTAL UART
[
0
0
0
0
1
1
1
1
N
+2]
IMER
TMRCK
(16-bit Value)
B
/C
IT
T
[
OUNTER CIRCUIT
0
0
1
1
0
0
1
1
N
ABLE
+1]
Timer Interrupt Enable
Single/Re-triggerable
Clock
Select
Start/Stop
T
ABLE
5: UART C
1
0
B
IT
0
1
0
1
0
1
0
1
6: UART C
[
N
]
.
None
RXRDY and RX Line Status (logic OR of LSR[4:1])
RXRDY Time-out
TXRDY, THR or TSR (auto RS485 mode) empty
MSR, RTS/CTS or DTR/DSR delta or Xoff/Xon det. or special char. detected
Reserved.
MPIO pin(s). Available only within channel 0, reserved in other channels.
TIMER Time-out. Available only within channel 0, reserved in other chan-
nels.
Timer/Counter
HANNEL
16-Bit
HANNEL
[7:0] I
Re-trigger
15
[7:0] I
NTERRUPT
0
1
interrupt may be generated in the INT Register when
the timer times out. It is controlled through 4 configu-
ration registers [TIMERCNTL, TIMER, TIMELSB,
TIMERMSB]. These registers provide start/stop and
re-triggerable or one-shot operation. The time-out
output of the Timer can be set to generate an inter-
rupt for system or event alarm.
Time-out
Single-shot
NTERRUPT
I
NTERRUPT
S
1
0
OURCE
C
No Interrupt
Timer Interrupt, Ch-0 INT=7
LEARING
E
S
NCODING
OURCE
1
0
:
(
S
)
MPIOLVL[0]
MPIO[0]
PRELIMINARY