LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 10

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table 7.9 - Channel/Data Commands supported in ECP mode .................................................................................108
Table 7.10 - I/O Address Map ....................................................................................................................................115
Table 7.11 - Host Interface Flags ...............................................................................................................................116
Table 7.12 - Status Register ......................................................................................................................................118
Table 7.13 - Keyboard and Mouse Pin/Register Reset Values ..................................................................................119
Table 7.14 - Keyboard Port 92 Register.....................................................................................................................120
Table 7.15 - nA20M Truth Table ................................................................................................................................121
Table 7.16 - GPIO Summary......................................................................................................................................125
Table 7.17 - General Purpose I/O Port Assignments .................................................................................................126
Table 7.18 - GPIO Configuration Summary ...............................................................................................................126
Table 7.19 - GPIO Read/Write Behavior ....................................................................................................................127
Table 7.20 - Hard Drive Front Panel Pins ..................................................................................................................132
Table 7.21 - nHD_LED Truth Table............................................................................................................................132
Table 7.22 - LED Pins ................................................................................................................................................133
Table 7.23 - LED Truth Table.....................................................................................................................................133
Table 7.24 - Reference Generation Pins....................................................................................................................134
Table 7.25 - REF5V ...................................................................................................................................................135
Table 7.26 - REF5V_STBY ........................................................................................................................................135
Table 7.27 - nIDE_RSTDRV Pin ................................................................................................................................136
Table 7.28 - nIDE_RSTDRV Truth Table ...................................................................................................................136
Table 7.29 - nPCIRST_OUT Pins ..............................................................................................................................137
Table 7.30 - nPCIRST_OUT and nPCIRST_OUT2 Truth Table ................................................................................137
Table 7.31 - Voltage Translation DDC Pins ...............................................................................................................137
Table 7.32 - VGA DDCSDA Voltage Translation Logic ..............................................................................................138
Table 7.33 - VGA DDCSCL Voltage Translation Logic ..............................................................................................138
Table 7.34 - SMBus Isolation Pins .............................................................................................................................139
Table 7.35 - SMB_CLK Isolation Logic ......................................................................................................................140
Table 7.36 - SMB_DAT Isolation Logic ......................................................................................................................140
Table 7.37 - nPS_ON, nCPU_PRESENT and nSLP_S3 Pins ...................................................................................141
Table 7.38 - nPS_ON Truth Table..............................................................................................................................141
Table 7.39 - PWRGD_3V, nFPRST and PWRGD_PS Pins .......................................................................................141
Table 7.40 - PWRGD_3V Truth Table........................................................................................................................142
Table 7.41 - SCK_BJT_GATE Pin .............................................................................................................................143
Table 7.42 - SCK_BJT_GATE Truth Table ................................................................................................................143
Table 7.43 - nBACKFEED_CUT and LATCHED_BF_CUT Pins ................................................................................144
Table 7.44 - nBACKFEED_CUT Truth Table .............................................................................................................144
Table 7.45 - LATCHED_BF_CUT Truth Table ...........................................................................................................145
Table 7.46 - Latched Backfeed Cut Power Up Sequence Timing ..............................................................................146
Table 7.47 - Latched Backfeed Cut Sequence 1 and 2 Timing ..................................................................................147
Table 7.48 - nRSMRST Pin........................................................................................................................................149
Table 7.49 - CNR Pins ...............................................................................................................................................149
Table 7.50 - CNR Logic Truth Table ..........................................................................................................................150
Table 8.1 - Power Control Runtime Registers Summary, LD_NUM Bit = 0................................................................151
Table 8.2 - Power Control Runtime Registers Description, LD_NUM Bit = 0 .............................................................152
Table 9.1 - GPIO Runtime Registers Summary, LD_NUM = 0...................................................................................158
Table 9.2 - GPIO Runtime Registers Description, LD_NUM = 0 ................................................................................159
Table 10.1 - Runtime Register Block Runtime Registers Summary ...........................................................................162
Table 10.2 - Runtime Register Block Runtime Registers Description ........................................................................163
Table 11.1 - LPC47M172 Configuration Registers Summary, LD_NUM bit = 0 .........................................................176
Table 11.2 - LPC47M172 Configuration Register Summary, LD_NUM=1..................................................................178
Table 11.3 - Chip Level Registers ..............................................................................................................................180
Table 11.4 - Logical Device Registers........................................................................................................................183
Table 11.5 - Primary Interrupt Select Configuration Register Description ..................................................................185
Table 11.6 - DMA Channel Select Configuration Register Description ......................................................................185
Table 11.7 - Logical Device I/O Address, LD_NUM Bit = 0 ........................................................................................187
Table 11.8 - Logical Device I/O Address, LD_NUM Bit = 1 .......................................................................................188
Table 11.9 - Floppy Disk Controller Logical Device Configuration Registers .............................................................190
Table 11.10 - Serial Port 2 Logical Device Configuration Registers...........................................................................191
Table 11.11 - Parallel Port Logical Device Configuration Registers ...........................................................................192
Table 11.12 - Serial Port 1 Logical Device Configuration Registers...........................................................................193
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Page 10
SMSC LPC47M172
DATASHEET