LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 4

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
Table Of Contents
LPC47M172 Datasheet Revision History ................................................................................................. 3
Chapter 1
Chapter 2
Chapter 3
Chapter 4
Chapter 5
Chapter 6
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
3.1
3.2
3.3
3.4
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
6.1
6.2
6.3
6.4
6.5
6.6
6.7
5.3.1
5.5.1
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.3.9
6.3.10
6.3.11
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.4.7
6.4.8
6.4.9
6.4.10
6.4.11
6.4.12
6.5.1
6.5.2
6.5.3
6.7.1
6.7.2
Buffer Name Descriptions ..........................................................................................................................23
Pins With Internal Resistors .......................................................................................................................24
Pins That Require External Resistors.........................................................................................................24
Default State of Pins...................................................................................................................................25
3 Volt Operation / 5 Volt Tolerance ............................................................................................................30
VCC Power ................................................................................................................................................30
VTR Power.................................................................................................................................................30
V5P0_STBY Power ....................................................................................................................................31
32.768 kHz Trickle Clock Input...................................................................................................................31
14.318 MHz Clock Input .............................................................................................................................32
Internal PWRGOOD ...................................................................................................................................32
Maximum Current Values...........................................................................................................................32
Power Management Events (PME/SCI) .....................................................................................................32
Super I/O Registers....................................................................................................................................33
Host Processor Interface (LPC) .................................................................................................................34
LPC Interface .............................................................................................................................................34
Floppy Disk Controller ................................................................................................................................38
Modes of Operation....................................................................................................................................52
DMA Transfers ...........................................................................................................................................52
Controller Phases.......................................................................................................................................53
General Description.............................................................................................................. 12
Pin Layout ............................................................................................................................ 13
Description of Pin Functions ................................................................................................ 15
Block Diagram ...................................................................................................................... 29
Power and Clock Functionality............................................................................................. 30
Trickle Power Functionality .................................................................................................................31
Indication of 32KHZ Clock...................................................................................................................31
Functional Description.......................................................................................................... 33
LPC Interface Signal Definition ...........................................................................................................34
LPC Cycles .........................................................................................................................................34
Field Definitions...................................................................................................................................34
NLFRAME Usage................................................................................................................................35
I/O Read and Write Cycles..................................................................................................................35
DMA Read and Write Cycles ..............................................................................................................35
DMA Protocol ......................................................................................................................................35
Power Management ............................................................................................................................36
SYNC Protocol ....................................................................................................................................36
FDC Configuration Registers ..............................................................................................................38
FDC Internal Registers........................................................................................................................38
Status Register A (SRA) .....................................................................................................................39
Status Register B (SRB) .....................................................................................................................40
Digital Output Register (DOR).............................................................................................................42
Tape Drive Register (TDR) .................................................................................................................43
Data Rate Select Register (DSR)........................................................................................................44
Main Status Register...........................................................................................................................46
Data Register (FIFO)...........................................................................................................................47
PC/AT Mode .......................................................................................................................................52
PS/2 Mode ..........................................................................................................................................52
Model 30 Mode ...................................................................................................................................52
Command Phase ................................................................................................................................53
Execution Phase .................................................................................................................................53
I/O and DMA START Fields.............................................................................................................37
LPC Transfers .................................................................................................................................37
Digital Input Register (DIR)..............................................................................................................48
Configuration Control Register (CCR) .............................................................................................49
Status Register Encoding ................................................................................................................50
DATASHEET
Page 4
SMSC LPC47M172