LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 128
![no-image](/images/no-image-200.jpg)
LPC47M172
Manufacturer Part Number
LPC47M172
Description
ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
Manufacturer
SMSC Corporation
Datasheet
1.LPC47M172.pdf
(227 pages)
- Current page: 128 of 227
- Download datasheet (2Mb)
Advanced I/O Controller with Motherboard GLUE Logic
Datasheet
7.27.5 GPIO PME Functionality
7.27.6 Either Edge Triggered Interrupts
7.28
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
The LPC47M172 provides 12 GPIOs that can directly generate a PME. See the Table 7.16. The polarity
bit in the GPIO control registers select the edge on these GPIO pins that will set the associated status bit
in the PME_STS2 and PME_STS3 registers. The default is the low-to-high edge. If the corresponding
enable bit in the PME_EN2 and PME_EN3 registers and the PME_EN bit in the PME_EN register is set, a
PME will be generated. The PME registers are runtime registers which are located at the address
contained in the configuration registers 0x60 and 0x61 in Power Control/Runtime Register Block Logical
Device. See GPIO Runtime Registers section when LD_NUM=0 and Chapter 10 Runtime Register Block
Runtime Registers when LD_NUM=1.The PME status bits for the GPIOs are cleared on a write of ‘1’.
The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and
enable registers:
GP10-GP17
GP20-GP23
The following PME status and enable registers for these GPIOs:
PME_STS2 and PME_EN2 for GP10-GP17
PME_STS3 and PME_EN3 for GP20-GP23
GP21 and GP22 are implemented such that they allow an PME interrupt to be generated on both a high-
to-low and a low-to-high edge transition, instead of one or the other as selected by the polarity bit.
The either edge triggered interrupts (EETI) function as follows: If the EETI function is selected for the
GPIO pin, then the bits that control input/output, polarity and open drain/push-pull have no effect on the
function of the pin. However, the polarity bit does affect the value of the GP bit (i.e., register GP2, bit 2 for
GP22).
A PME interrupt occurs if the PME enable bit is set for the corresponding GPIO and the EETI function is
selected on the GPIO. The PME status bit is set when the EETI pin transitions (on either edge) and are
cleared on a write of ‘1’. There are also status bits for the EETIs located in the MSC_STS register, which
are also cleared on a write of ‘1’. The MSC_STS register provides the status of all of the EETI interrupts
within one register. The PME or MSC status is valid whether or not the interrupt is enabled and whether or
not the EETI function is selected for the pin.
The MSC_STS register is defined in GPIO Runtime Registers section when LD_NUM=0 and Chapter 10
Runtime Register Block Runtime Registers when LD_NUM=1.
PME Support
The LPC47M172 offers support for power management events (PMEs), also referred to as a System
Control Interrupt (SCI) events in an ACPI system. A power management event is indicated to the chipset
via the assertion of the nIO_PME signal.
transitions on the ring indicator inputs nRI1 and nRI2, active keyboard-data edges, active mouse-data
edges, programmable edges on GPIO pins and fan tachometer event. The nIO_PME pin, can be
programmed to be active high or active low via the polarity bit in the nIO_PME Register. The output buffer
type of the pin can be programmed to be open-drain or push-pull via bit 7 of the nIO_PME Register. The
nIO_PME pin function defaults to active low, open-drain output. The nIO_PME Register is located at an
offset 0x16 from Power Control/Runtime Register Block logical device base address. See Chapter 8
Power Control Runtime Registers and Chapter 10 Runtime Register Block Runtime Registers.
DATASHEET
Page 128
In the LPC47M172, the nIO_PME is asserted by active
SMSC LPC47M172
Related parts for LPC47M172
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![LPC-20-SPEC](/images/no-image3.png)
Part Number:
Description:
20w Single Output Swi Tching Power Supply Lpc-20 Ser I Es
Manufacturer:
Analog Technology, Inc.
Datasheet:
![LPC-LP-0.8DQEW](/images/no-image3.png)
Part Number:
Description:
Low-profile Coaxial Connectors
Manufacturer:
DDK Ltd.
Datasheet:
![LAN83C183-JD](/images/no-image3.png)
Part Number:
Description:
FAST ETHERNET PHYSICAL LAYER DEVICE
Manufacturer:
SMSC Corporation
Datasheet:
![FDC37N769TQFP](/images/no-image3.png)
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
![LPC47M102S-MC](/images/no-image3.png)
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
![LPC47N267-MN](/images/no-image3.png)
Part Number:
Description:
357-036-542-201 CARDEDGE 36POS DL .156 BLK LOPRO
Manufacturer:
SMSC Corporation
Datasheet:
![USB20H04-JD](/images/no-image3.png)
Part Number:
Description:
4-PORT USB2.0 HUB CONTROLLER
Manufacturer:
SMSC Corporation
Datasheet:
![FDC37M602](/images/no-image3.png)
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
![FDC37B777](/images/no-image3.png)
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
![FDC37C672](/images/no-image3.png)
Part Number:
Description:
FDC37C672ENHANCED SUPER I/O CONTROLLER WITH FAST IR
Manufacturer:
SMSC Corporation
Datasheet:
![COM90C66LJP](/images/no-image3.png)
Part Number:
Description:
COM90C66LJPARCNET Controller/Transceiver with AT Interface and On-Chip RAM
Manufacturer:
SMSC Corporation
Datasheet:
![FDC37N869TQFP](/images/no-image3.png)
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
![USB97C100QFP](/images/no-image3.png)
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet:
![LPC47N227-MN](/images/no-image3.png)
Part Number:
Description:
Manufacturer:
SMSC Corporation
Datasheet: