LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 17

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
16
17
18
19
20
21
22
23
24
25
PIN#
nSTEP
nDIR
nDS0
nMTR0
nINDEX
DRVDEN1
DRVDEN0
nDCD1
nDSR1
RXD1
(NOTE 1)
NAME
Step Pulse Output. This active low high
current driver issues a low pulse for each
track-to-track movement of the head.
Can be configured as an Open-Drain
Output.
Step Direction Output. This high current
low active output determines the direction
of the head movement. A logic “1” on this
pin means outward motion, while a logic
“0” means inward motion. Can be
configured as an Open-Drain Output.
Drive Select 0 Output. Can be configured
as an Open-Drain Output.
Motor On 0 Output. Can be configured as
an Open-Drain Output.
This active low Schmitt Trigger input
senses from the disk drive that the head
is positioned over the beginning of a
track, as marked by an index hole.
Drive Density Select 1 Output. Indicates
the drive and media selected. Can be
configured as Open-Drain Output.
Drive Density Select 0 Output. Indicates
the drive and media selected. Can be
configured as Open-Drain Output.
Active low Data Carrier Detect input for
the serial port. Handshake signal that
notifies the UART that carrier signal is
detected by the modem. The CPU can
monitor the status of nDCD signal by
reading bit 7 of Modem Status Register
(MSR). A nDCD signal state change from
low to high after the last MSR read will set
MSR bit 3 to a 1. If bit 3 of Interrupt
Enable Register is set, the interrupt is
generated when nDCD changes state.
Note: Bit 7 of MSR is the complement of
nDCD.
Active low Data Set Ready input for the
serial port. Handshake signal that notifies
the UART that the modem is ready to
establish the communication link. The
CPU can monitor the status of nDSR
signal by reading bit 5 of Modem Status
Register (MSR). A nDSR signal state
change from low to high after the last
MSR read will set MSR bit 1 to a 1. If bit
3 of Interrupt Enable Register is set, the
interrupt is generated when nDSR
changes state.
Note: Bit 5 of MSR is the complement of
nDSR.
Receiver serial data input.
SERIAL PORT 1 INTERFACE (8)
DESCRIPTION
DATASHEET
Page 17
Advanced I/O Controller with Motherboard GLUE Logic
O12
O12
O12
O12
IS
O12
O12
I
I
IS
(NOTE 2)
BUFFER
NAME
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
(NOTE 3)
WELL
PWR
SMSC LPC47M172
NOTES
Datasheet