LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 155

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

SMSC LPC47M172
Keyboard Scan
Code
Default = 0x00
Tach1 LSB
Default = 0x00 on
VTR POR
Tach1 MSB
Default = 0x00 on
VTR POR
Tach2 LSB
Default = 0x00 on
VTR POR
Tach2 MSB
Default = 0x00 on
VTR POR
nIO_PME Register
Default = 0x80 on
VTR POR
MSC_STS
Default = 0x00
on VTR POR
on VTR POR
NAME
REG OFFSET
(Type)
(R/W)
(R/W)
(R/W)
0x17
0x11
0x12
0x13
0x14
0x15
0x16
(R)
(R)
(R)
(R)
DATASHEET
Keyboard Scan Code
Bit[0] LSB of Scan Code
Bit[7] MSB of Scan Code
This register is least significant 8-bit of the 16-bit Fan
Tachometer 1 reading.
Bit[0] FAN_TACH1 Reading Bit 0
…
Bit[7] FAN_TACH1 Reading Bit 7
This register is most significant 8-bit of the 16-bit Fan
Tachometer 1 reading.
Bit[0] FAN_TACH1 Reading Bit 8
…
Bit[7] FAN_TACH1 Reading Bit 15
This register is least significant 8-bit of the 16-bit Fan
Tachometer 2 reading.
Bit[0] FAN_TACH2 Reading Bit 0
…
Bit[7] FAN_TACH2 Reading Bit 7
This register is most significant 8-bit of the 16-bit Fan
Tachometer 2 reading.
Bit[0] FAN_TACH2 Reading Bit 8
…
Bit[7] FAN_TACH2 Reading Bit 15
Bit[0] Reserved
Bit[1] Polarity : =1 Invert, =0 No Invert
Bits[6:2] Reserved
Bit[7] Output Type Select
1=Open Drain (default)
0=Push Pull
Miscellaneous Status Register
Bits[1:0] can be cleared by writing a 1 to their position
(writing a 0 has no effect).
Bit[0] Either Edge Triggered Interrupt Input 0 Status. This
bit is set when an edge occurs on the GP21 pin.
Bit[1] Either Edge Triggered Interrupt Input 1 Status. This
bit is set when an edge occurs on the GP22 pin.
Bit[7:2] Reserved. This bit always returns zero.
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Page 155
DESCRIPTION
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Datasheet