LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 163

• Manufacturer Part Number: LPC47M172
• Description: ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
• Manufacturer: SMSC Corporation

SMSC LPC47M172
PME_STS
Default = 0x00
on VTR POR
N/A
PME_EN
Default = 0x00
on VTR POR
N/A
REGISTER
OFFSET
(HEX)
2D-34
37-3F
2C
25
26
27
28
29
2A
2B
35
36
NAME
TYPE
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
Table 10.2 - Runtime Register Block Runtime Registers Description
REG OFFSET
0x01 – 0x03
0x05 – 0x07
PCI RESET
(Type)
(R/W)
(R/W)
0x00
0x04
(R)
(R)
-
-
-
-
-
-
-
-
-
-
-
-
VCC POR
Bit[0] PME_Status
= 0 (default)
= 1 Set when LPC47M172 would normally assert the nIO_PME signal,
Bit[7:1] Reserved
PME_Status is not affected by Vcc POR, SOFT RESET or HARD RESET.
Writing a “1” to PME_Status will clear it and cause the LPC47M172 to stop
asserting nIO_PME, in enabled. Writing a “0” to PME_Status has no effect.
Bits[7:0] Reserved – reads return 0
Bit[0] PME_En
= 0
= 1
Bit[7:1] Reserved
PME_En is not affected by Vcc POR, SOFT RESET or HARD RESET
Bits[7:0] Reserved – reads return 0
DATASHEET
-
-
-
-
-
-
-
-
-
-
-
-
independent of the state of the PME_En bit.
nIO_PME signal assertion is disabled (default)
Enables LPC47M172 to assert nIO_PME signal
VTR POR
Page 163
0x01
0x01
0x01
0x04
0x04
0x04
0x04
0x05
0x00
0x00
-
-
RESET
SOFT
DESCRIPTION
-
-
-
-
-
-
-
-
-
-
-
-
Advanced I/O Controller with Motherboard GLUE Logic
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
GP15
GP16
GP17
GP20
GP21
GP22
GP23
GP24
Reserved – reads return 0
GP1
GP2
Reserved – reads return 0
REGISTER
Datasheet