LPC47M172 SMSC Corporation, LPC47M172 Datasheet - Page 127
LPC47M172
Manufacturer Part Number
LPC47M172
Description
ADVANCED I/O CONTROLLER WITH MOTHERBOARD GLUE LOGIC
Manufacturer
SMSC Corporation
Datasheet
1.LPC47M172.pdf
(227 pages)
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7.27.4 GPIO Operation
Note:
SMSC LPC47M172
GPx_nIOW
GPx_nIOR
HOST OPERATION
The operation of the GPIO ports is illustrated in Figure 7.4.
Figure 7.4 is for illustration purposes only and is not intended to suggest specific implementation details.
When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the
inverted or non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed
as an input has no effect (Table 7.19)
When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been
written into the GPIO data register is output to the GPIO pin.
programmed as an output returns the last value written to the data register (Table 7.19). When the GPIO
is programmed as an output, the pin is excluded from the PME logic.
WRITE
READ
SD-bit
Data Register
Transparen
D-TYPE
D
Q
Bit-n
GPIO
t
LATCHED VALUE OF GPIO PIN
NO EFFECT
Q
D
GPIO INPUT PORT
Table 7.19 - GPIO Read/Write Behavior
Figure 7.4 - GPIO Function Illustration
0
1
DATASHEET
Page 127
GPIO
Configuration
Register bit-1
(Polarity)
LAST WRITE TO GPIO DATA REGISTER
BIT PLACED IN GPIO DATA REGISTER
Advanced I/O Controller with Motherboard GLUE Logic
GPIO OUTPUT PORT
SMSC/Non-SMSC Register Sets (Rev. 02-27-04)
Reading from a GPIO port that is
GPIO
Configuration
Register bit-0
(Input/Output)
GPIO
PIN
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