PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 13

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

TABLE 2-1
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Note 1: These registers can be addressed from either bank.
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Addr
1998 Microchip Technology Inc.
Bank 0
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.
4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
6: The IRP and RP1 bits are reserved. Always maintain these bits clear.
7: On any device reset, these pins are configured as inputs.
8: This is the value that will be in the port output latch.
Name
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
ADCON0
Shaded locations are unimplemented, read as '0'.
are transferred to the upper byte of the program counter.
(1)
(1)
(1)
(7)
(8)
(3,8)
(8)
(3,8)
(4)
(1)
(1,2)
(1)
(4)
SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Latch when written: PORTB pins when read
PORTC Data Latch when written: PORTC pins when read
PORTD Data Latch when written: PORTD pins when read
Holding register for the Least Significant Byte of the 16-bit TMR1 register
Holding register for the Most Significant Byte of the 16-bit TMR1 register
Timer2 module’s register
Synchronous Serial Port Receive Buffer/Transmit Register
Capture/Compare/PWM Register1 (LSB)
Capture/Compare/PWM Register1 (MSB)
USART Transmit Data Register
USART Receive Data Register
Capture/Compare/PWM Register2 (LSB)
Capture/Compare/PWM Register2 (MSB)
A/D Result Register
PSPIF
ADCS1
WCOL
SPEN
IRP
Bit 7
GIE
—
—
—
—
—
—
—
—
(6)
(3)
TOUTPS3 TOUTPS2
SSPOV
ADCS0
ADIF
RP1
PEIE
Bit 6
RX9
—
—
—
—
—
—
—
(6)
(4)
PORTA Data Latch when written: PORTA pins when read
T1CKPS1
SSPEN
CCP1X
CCP2X
SREN
CHS2
RCIF
Bit 5
T0IE
RP0
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
T1CKPS0
TOUTPS1
CCP1Y
CCP2Y
CREN
PIC16C63A/65B/73B/74B
CHS1
INTE
TXIF
Bit 4
CKP
TO
—
–
T1OSCEN
TOUTPS0
CCP1M3
CCP2M3
SSPM3
SSPIF
CHS0
RBIE
Bit 3
PD
—
—
—
GO/DONE
TMR2ON
T1SYNC
CCP1M2
CCP2M2
CCP1IF
SSPM2
FERR
Bit 2
T0IF
RE2
—
Z
T2CKPS1
TMR1CS
CCP1M1
CCP2M1
TMR2IF
SSPM1
OERR
INTF
Bit 1
RE1
DC
—
—
T2CKPS0 -000 0000 -000 0000
TMR1ON
CCP1M0
CCP2M0
TMR1IF
CCP2IF
SSPM0
ADON
RX9D
RBIF
Bit 0
RE0
C
DS30605A-page 13
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
--0x 0000 --0u 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
---- -xxx ---- -uuu
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --uu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
0000 00-0 0000 00-0
Value on
POR,
BOR
other resets
Value on all
(5)