PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 70

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC16C63A/65B/73B/74B
9.3
In Synchronous Master mode, the data is transmitted in
a half-duplex manner, i.e. transmission and reception
do not occur at the same time. When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA<4>). In
addition, enable bit SPEN (RCSTA<7>) is set in order
to configure the RC6/TX/CK and RC7/RX/DT I/O pins
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA<7>).
9.3.1
The USART transmitter block diagram is shown in
Figure 9-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer register
TXREG. The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one Tcycle), the TXREG is empty and inter-
rupt bit TXIF (PIR1<4>) is set. The interrupt can be
TABLE 9-8:
DS30605A-page 70
Address
0Ch
18h
19h
8Ch
98h
99h
Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear.
USART Synchronous Master Mode
USART SYNCHRONOUS MASTER
TRANSMISSION
Name
PIR1
RCSTA
TXREG
PIE1
TXSTA
SPBRG Baud Rate Generator Register
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
PSPIF
SPEN
USART Transmit Register
PSPIE
CSRC
Bit 7
(1)
(1)
ADIF
RX9
ADIE
TX9
Bit 6
(2)
(2)
RCIF
SREN
RCIE
TXEN
Bit 5
TXIF
CREN —
TXIE
SYNC
Bit 4
SSPIF
SSPIE
—
Bit 3
CCP1IF
FERR
CCP1IE
BRGH
enabled/disabled by setting/clearing enable bit TXIE
(PIE1<4>). Flag bit TXIF will be set regardless of the
state of enable bit TXIE and cannot be cleared in soft-
ware. It will reset only when new data is loaded into the
TXREG register. While flag bit TXIF indicates the status
of the TXREG register, another bit TRMT (TXSTA<1>)
shows the status of the TSR register. TRMT is a read
only bit which is set when the TSR is empty. No inter-
rupt logic is tied to this bit, so the user has to poll this
bit in order to determine if the TSR register is empty.
The TSR is not mapped in data memory so it is not
available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Bit 2
Initialize the SPBRG register for the appropriate
baud rate (Section 9.1).
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
If interrupts are desired, then set enable bit
TXIE.
If 9-bit transmission is desired, then set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREG register.
TMR2IF
OERR
TMR2IE
TRMT
Bit 1
TMR1IF
RX9D
TMR1IE
TX9D
Bit 0
1998 Microchip Technology Inc.
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on
POR,
BOR
other Resets
Value on all
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000