PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 90

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC16C63A/65B/73B/74B
11.10
The PIC16CXX family has up to 12 sources of interrupt.
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 11-11: INTERRUPT LOGIC
DS30605A-page 90
Note:
The following table shows which devices have which interrupts.
PIC16C63A
PIC16C65B
PIC16C73B
PIC16C74B
PSPIF
PSPIE
CCP2IF
CCP2IE
Device
Interrupts
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
ADIF
ADIE
TMR1IF
TMR1IE
T0IF
Yes
Yes
Yes
Yes
RCIF
RCIE
TMR2IF
TMR2IE
INTF
Yes
Yes
Yes
Yes
TXIF
TXIE
SSPIF
SSPIE
CCP1IF
CCP1IE
RBIF
Yes
Yes
Yes
Yes
PSPIF
Yes
Yes
-
-
ADIF
Yes
Yes
-
-
RCIF
Yes
Yes
Yes
Yes
TXIF
T0IF
T0IE
INTF
INTE
RBIF
RBIE
PEIE
GIE
Yes
Yes
Yes
Yes
The RB0/INT pin interrupt, the RB port change inter-
rupt and the TMR0 overflow interrupt flags are con-
tained in the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2, and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set regardless of the status of
their corresponding mask bit or the GIE bit.
SSPIF
Yes
Yes
Yes
Yes
CCP1IF
Yes
Yes
Yes
Yes
TMR2IF
Yes
Yes
Yes
Yes
1998 Microchip Technology Inc.
Wake-up (If in SLEEP mode)
TMR1IF
Yes
Yes
Yes
Yes
Interrupt to CPU
CCP2IF
Yes
Yes
Yes
Yes