PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 35

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PIC16C63A

Manufacturer Part Number
PIC16C63A
Description
28/40-Pin 8-Bit CMOS Microcontrollers
Manufacturer
Microchip Technology
Datasheet

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3.6
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC16C65B and PIC16C74B).
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit PSPMODE
(TRISE<4>) is set. In slave mode it is asynchronously
readable and writable by the external world through RD
control input pin RE0/RD and WR control input pin
RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). For the
PIC16C74B,
PCFG2:PCFG0 (ADCON1<2:0>) must be set, which
will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS
PORTD<7:0>
1998 Microchip Technology Inc.
PSPIF
Parallel Slave Port
OBF
CS
WR
RD
IBF
the
Q1
A/D
port
Q2
configuration
Q3
Q4
bits
Q1
PIC16C63A/65B/73B/74B
Q2
FIGURE 3-9:
One bit of PORTD
Data bus
Note: I/O pin has protection diodes to V
Set interrupt flag
PSPIF (PIR1<7>)
Q3
WR
PORT
RD
PORT
Q4
Q
D
CK
PORTD AND PORTE BLOCK
DIAGRAM (PARALLEL
SLAVE PORT)
EN
Q1
EN
Q
D
Q2
Chip Select
Read
Write
Q3
DS30605A-page 35
TTL
DD
TTL
TTL
TTL
and V
Q4
SS
RD
CS
WR
RDx
pin
.

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