PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 14

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC16C63A/65B/73B/74B
TABLE 2-1
DS30605A-page 14
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Note 1: These registers can be addressed from either bank.
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Addr
Bank 1
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.
4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
6: The IRP and RP1 bits are reserved. Always maintain these bits clear.
7: On any device reset, these pins are configured as inputs.
8: This is the value that will be in the port output latch.
Name
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
Shaded locations are unimplemented, read as '0'.
are transferred to the upper byte of the program counter.
(1)
(1)
(1)
—
—
—
—
—
—
—
—
—
—
—
(3)
(3)
(1)
(1,2)
(1)
(4)
SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
PORTD Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Baud Rate Generator Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
PSPIE
RBPU
CSRC
IRP
SMP
Bit 7
GIE
IBF
—
—
—
—
—
(6)
(3)
INTEDG
ADIE
RP1
PEIE
Bit 6
OBF
CKE
TX9
—
—
—
—
—
(6)
(4)
PORTA Data Direction Register
2
C mode) Address Register
T0CS
TXEN
IBOV
RCIE
Bit 5
T0IE
RP0
D/A
—
—
—
—
Write Buffer for the upper 5 bits of the Program Counter
PSPMODE
SYNC
T0SE
INTE
TXIE
Bit 4
TO
—
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
—
—
—
S
PORTE Data Direction Bits
CCP1IE
PCFG2
BRGH
Bit 2
T0IF
PS2
R/W
—
—
Z
TMR2IE
PCFG1
TRMT
Bit 1
INTF
POR
PS1
DC
UA
—
1998 Microchip Technology Inc.
TMR1IE
CCP2IE
PCFG0
TX9D
RBIF
BOR
Bit 0
PS0
BF
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
rr01 1xxx rr0q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
---- ---0 ---- ---0
---- --qq ---- --uu
1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0000 -010 0000 -010
0000 0000 0000 0000
---- -000
Value on
POR,
BOR
—
—
—
—
—
—
—
—
—
—
—
other resets
Value on all
---- -000
(5)
—
—
—
—
—
—
—
—
—
—
—