PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 77

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

The ADRES register contains the result of the A/D con-
version. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF is set. The block diagram of the A/D module is
shown in Figure 10-3.
The value that is in the ADRES register is not modified
for a Power-on Reset. The ADRES register will contain
unknown data after a Power-on Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 10.1.
After this acquisition time has elapsed the A/D conver-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
1.
FIGURE 10-3: A/D BLOCK DIAGRAM
1998 Microchip Technology Inc.
Note 1: Available on the PIC16C74B only.
Configure the A/D module:
• Configure analog pins / voltage reference /
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
and digital I/O (ADCON1)
Converter
A/D
(Reference
voltage)
V
REF
(Input voltage)
PCFG2:PCFG0
V
IN
PIC16C63A/65B/73B/74B
V
DD
001 or
011 or
101
000 or
010 or
100
2.
3.
4.
5.
6.
7.
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
OR
• Waiting for the A/D interrupt
Read A/D Result register (ADRES), clear bit
ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as T
required before next acquisition starts.
CHS2:CHS0
111
110
101
100
011
010
001
000
AD
. A minimum wait of 2T
RE2/AN7
RA2/AN2
RA1/AN1
RA0/AN0
DS30605A-page 77
RE1/AN6
RE0/AN5
RA5/AN4
RA3/AN3/V
(1)
(1)
(1)
REF
AD
is