PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 57

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

8.3.1.1
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condi-
tion, the 8-bits are shifted into the SSPSR register. All
incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
In 10-bit address mode, two address bytes need to be
received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. Bit R/W (SSPSTAT<2>) must specify a write
so the slave device will receive the second address
byte. For a 10-bit address the first byte would equal
TABLE 8-2:
Note:
1998 Microchip Technology Inc.
Transfer is Received
Status Bits as Data
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
BF
0
1
1
0
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
ADDRESSING
SSPOV
DATA TRANSFER RECEIVED BYTE ACTIONS
0
0
1
1
SSPSR
Yes
Yes
No
No
SSPBUF
PIC16C63A/65B/73B/74B
‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs
of the address. The sequence of events for 10-bit
address is as follows with steps 7- 9 for slave-transmit-
ter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Generate ACK
Receive first (high) byte of Address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of Address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of Address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address. If match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive repeated START condition.
Receive first (high) byte of Address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Pulse
Yes
No
No
No
(SSP Interrupt occurs
Set bit SSPIF
if enabled)
Yes
Yes
Yes
Yes
DS30605A-page 57