PIC16C63A Microchip Technology, PIC16C63A Datasheet - Page 72

• Manufacturer Part Number: PIC16C63A
• Description: 28/40-Pin 8-Bit CMOS Microcontrollers
• Manufacturer: Microchip Technology

PIC16C63A/65B/73B/74B
9.3.2
Once synchronous mode is selected, reception is
enabled by setting either enable bit SREN (RCSTA<5>)
or enable bit CREN (RCSTA<4>). Data is sampled on
the RC7/RX/DT pin on the falling edge of the clock. If
enable bit SREN is set, then only a single word is
received. If enable bit CREN is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
Steps to follow when setting up a Synchronous Master
Reception:
1.
2.
TABLE 9-9:
FIGURE 9-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
DS30605A-page 72
Address
0Ch
18h
1Ah
8Ch
98h
99h
Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception.
Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear.
RC7/RX/DT pin
RC6/TX/CK pin
Initialize the SPBRG register for the appropriate
baud rate. (Section 9.1)
Enable the synchronous master serial port by
setting bits SYNC, SPEN, and CSRC.
2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Allways maintain these bits clear.
USART SYNCHRONOUS MASTER
RECEPTION
Write to
bit SREN
SREN bit
CREN bit
RCIF bit
(interrupt)
Read
RXREG
Name
PIR1
RCSTA
RCREG USART Receive Register
PIE1
TXSTA
SPBRG
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
'0'
Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'.
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PSPIF
SPEN
PSPIE
CSRC
Baud Rate Generator Register
Bit 7
(1)
(1)
ADIF
RX9
ADIE
TX9
Bit 6
bit0
(2)
(2)
RCIF
SREN
RCIE
TXEN
Bit 5
Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit1
TXIF
CREN —
TXIE
SYNC
Bit 4
bit2
SSPIF
SSPIE CCP1IE TMR2IE
—
Bit 3
bit3
CCP1IF
FERR
BRGH
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
Bit 2
Ensure bits CREN and SREN are clear.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
If a single reception is required, set bit SREN.
For continuous reception, set bit CREN.
Interrupt flag bit RCIF will be set when reception
is complete and an interrupt will be generated if
enable bit RCIE was set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit CREN.
bit4
TMR2IF
OERR
TRMT
Bit 1
bit5
TMR1IF
RX9D
TMR1IE
TX9D
Bit 0
bit6
1998 Microchip Technology Inc.
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
Value on:
POR,
BOR
bit7
other Resets
Q1 Q2 Q3 Q4
Value on all
0000 0000
0000 -00x
0000 0000
0000 0000
0000 -010
0000 0000
'0'