ISL9N306AD3ST Fairchild Semiconductor, ISL9N306AD3ST Datasheet - Page 5
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ISL9N306AD3ST
Manufacturer Part Number
ISL9N306AD3ST
Description
N-Channel Logic Level PWM Optimized UltraFET Trench Power MOSFETs 30V/ 50A/ 6m
Manufacturer
Fairchild Semiconductor
©2003 Fairchild Semiconductor Corporation
Typical Characteristic
Test Circuits and Waveforms
Figure 13. Switching Time vs Gate Resistance
VARY t
REQUIRED PEAK I
0V
Figure 11. Capacitance vs Drain to Source
Figure 15. Unclamped Energy Test Circuit
1000
5000
100
300
250
200
150
100
50
P
0
TO OBTAIN
0.1
0
V
V
V
t
GS
P
GS
GS
C
= 0V, f = 1MHz
= 4.5V, V
RSS
AS
R
C
V
GS
ISS
10
DS
, GATE TO SOURCE RESISTANCE ( )
C
, DRAIN TO SOURCE VOLTAGE (V)
DD
GD
C
GS
= 15V, I
Voltage
+ C
R
20
G
1
GD
D
t
t
r
d(ON)
= 16A
(Continued)
30
V
I
C
AS
DS
OSS
DUT
0.01
L
40
10
C
DS
t
d(OFF)
+ C
t
f
-
+
GD
V
DD
30
50
Figure 12. Gate Charge Waveforms for Constant
Figure 14. Switching Time vs Gate Resistance
0
10
Figure 16. Unclamped Energy Waveforms
8
6
4
2
0
500
400
300
200
100
0
0
V
0
DD
V
GS
= 15V
= 10V, V
10
R
GS
10
I
, GATE TO SOURCE RESISTANCE ( )
AS
DD
Gate Currents
Q
g
= 15V, I
20
, GATE CHARGE (nC)
t
P
20
D
t
d(OFF)
= 16A
30
BV
t
AV
DSS
t
WAVEFORMS IN
DESCENDING ORDER:
ISL9N306AD3 / ISL9N306AD3ST Rev. B2
f
30
I
I
I
D
D
D
t
r
40
= 50A
= 25A
= 5A
V
DS
40
50
t
V
d(ON)
DD
60
50