AD6426 Analog Devices, AD6426 Datasheet
AD6426
Available stocks
Related parts for AD6426
AD6426 Summary of contents
Page 1
... GSM 900 / DCS1800 / PCS1900 Mobile Stations (MS) Compliant to Phase 1 and Phase 2 specifications GENERAL DESCRIPTION The AD6426 Enhanced GSM Processor (EGSMP) is the central component of the highly integrated AD20msp425 GSM Chipset. Offering a low total chip count, low bill of materials cost and long talk and standby times, the chipset offers designers a straightforward route to a highly competitive product in the GSM/DCS1800 market ...
Page 2
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) ENHANCED GSM PROCESSOR AD6426 CALIBRATERADIO VDD(10) GND(10) Figure 2. External Interfaces of the AD6426 - 2 - AD6426 CLKIN VCTCXO OSC13MON OSCIN OSCOUT JTAGEN TCK ...
Page 3
... Radio Interface ................................................................35 High Speed Logging Interface ..........................................36 Data Interface ..................................................................37 Test Interface...................................................................38 EVBC Interface ASPORT ................................................39 EVBC Interface BSPORT ................................................40 EVBC Interface VSPORT ................................................41 Parallel Display Interface .................................................42 Serial Display Interface....................................................43 PACKAGING......................................................................44 LQFP Pin Locations.........................................................44 PBGA Pin Locations ........................................................45 LQFP Outline Dimensions ...............................................47 PBGA Outline Dimensions .............................................. AD6426 Confidential Information ...
Page 4
... EEPROM Clock / High Speed Logger Clock 1 O EEPROM Enable / High Speed Logger Frame Sync 1 O Display Controller Chip Select / Chip Enable 1 O LCD Control / Serial Display Data Output 1 O Backlight Control 6 I Keypad Row Inputs 4 O Keypad Column Strobes (open drain, pull low AD6426 Confidential Information ...
Page 5
... AGC Gain Select / General Purpose Output 19 1 1/O USC Ring Indicator / Serial Clock / GPO20 1 I USC Receive Data 1 O USC Transmit Data / Baseband Serial Port Data Input 1 I/O USC Clear to Send / Serial Frame Sync / GPI22 1 O USC Ready to Send / GPO21 - 5 - AD6426 Confidential Information ...
Page 6
... Power ON/OFF Control 1 I JTAG Enable 1 I JTAG Test Clock / HSL Data JTAG Test Mode Select / HSL Data 1 / DAI Reset 1 I JTAG Test Data Input / HSL Data 3 / DAI Data JTAG Test Data Output / HSL Data 2 / DAI Data AD6426 Confidential Information ...
Page 7
... This involves adding fixed patterns such as the tail bits and training sequence code. The resultant burst is written to the external Baseband Converter where the modulation is performed and the output timed to the system timebase before transmission AD6426 INTERLEAVE ENCRYPT VBC INTERFACE DECRYPT ...
Page 8
... The Channel Codec interfaces with the speech transcoder for speech traffic data and with an equalizer for recovered receive data. In the AD6426 the equalizer and speech transcoder are implemented in the DSP. Processor Sub-System The Processor Sub-System consists of a high performance 16- bit microcontroller together with a selection of peripheral elements ...
Page 9
... Preliminary Technical Information REGISTERS The AD6426 contains 88 Channel Codec Control Registers Peripheral Registers mapped into the Channel Codec address space starting at 8000h. All registers are normally accessed by the Layer 1 software provided with the AD20msp425 chipset. The user is not expected to read or write to any registers other than through the Layer 1 software ...
Page 10
... EVBC Tx Address Version Disable Synth. 0 Synt. Enable Sel IRQ4 Enable IRQ3 Enable IRQ4 active IRQ3 active GPIO8 OP En GPO17 Sel - 10 - AD6426 2 1 Encryption Type Encrypt Key Load Monitor Receive Transmit Enable Enable Enable Training Sequence Code Traffic Frame ...
Page 11
... R/W 101 8065h R/W 102 8066h R/W 103 8067h R/W 104 8068h R/W 105 8069h R 106 8074h R/W R/W R/W R R/W R/W R/W R/W R/W R/W R AD6426 Name DISPDDR W DISPCR R/W DDOR W DDIR R DRR R/W WDTR W MEM IF R/W PERST R/W PERCR R/W TAR R/W PERCLK R/W RTCTR1 R/W RTCTR2 R/W RTCTR3 R/W RTCTR4 R/W RTCTR5 R/W RTCAR1 R/W RTCAR2 R/W RTCAR3 R/W RTCCR R/W RTCSRZ ...
Page 12
... Out2 THRE Break Interrupt Framing Error DSR CTS DDCD SCR[7:0] CLOCK TX ENABLE CROSSPOINT SWITCH SDIROE IE SDIRIE Receive[15:8] Receive[7:0] Transmit[15:8] Transmit[7:0] Data[7: AD6426 BRR[3:0] DATEN CLKPOL CLKEN TEND ELSI ETBEI ERBFI InterruptID[2:0] Int Pend TX FIFO RX FIFO FIFO EN Stop Bits WLS[1:0] Out1 ...
Page 13
... DALLAS Test Key[7:0] USCCLK EN BUCLK EN FUCLK EN TR[1] TR[2] TR[3] TR[4] TR[5] AR[1] AR[2] AR[3] ALAWEN PWRUEN AGCENN ALARM APWRUP TXENABLE SERDISP MODE NMI - 13 - AD6426 DISP CLKEN CLK FREQ DDREMT RAM SEL7 DISP SRAM16 UA INT SSINT MONINT MONIE DSPPLL[2:0] FBENN Unused Unused OSCFAIL 32K PRESENT TESTOUT ...
Page 14
... Preliminary Technical Information GENERAL CONTROL Clocks Clock Input The AD6426 requires a single 13 MHz, low level clock signal, which has to be provided at the pin CLKIN. For proper operation a signal level of 250 mV minimum is required. PP This feature eases system design and reduces the need for external clock buffering ...
Page 15
... Capacitor in the range of 0.4F (maximum for ~24 hours standby) to 8mF (~30 minutes standby) Reset The AD6426 is reset by setting the RESET pin to GND. This will reset the H8-processor, the Channel Codec, the internal DSP as well as the LCD controller interface and Boot ROM logic. Both the DSP and the Channel Codec will be held in reset until the RESET register is written to by the H8 ...
Page 16
... Data Interface into the FLASH memory. This routine is activated by asserting the BOOTCODE pin. Power Control The AD6426 and Layer 1 software is optimized to minimize the mobile radio power consumption in all modes of operation. Two power control registers are dedicated for activating and deactivating functional modules: ...
Page 17
... FLASHPWD Disable to 1, the pin FLASHPWD becomes a general purpose output. The pin state is toggled by setting the GPO11 Data flag. To increase the flexibility of the AD6426, three pins in the Radio Interface are multiplexed within GPO functions. The pins multiplexed are: SYNTHEN1, AGCA and AGCB, with the default function being the Radio Interface ...
Page 18
... Mode This mode connects the synchronous data path to the SDIR/SDOR H8 Peripheral Control Registers, giving the H8 full access to the synchronous port bandwidth. This allows a fast synchronous communication to an external device, and is intended to be used for a fast download mechanism Confidential Information AD6426 ...
Page 19
... O Serial Display Clock Output By providing 4 keypad-column outputs (open drain, pull low) and 6 keypad-row inputs the AD6426 can monitor keys. Additionally, an extra column can be implemented by using the “ghost column” method for a total of 30 keys. The H8 processor is interrupted whenever a key is pressed. The KEYPADCOL pins are connected to the Keypad Column3-0 flags in the KEYPAD COLUMN CC Control Register 9 ...
Page 20
... Voiceband Serial Port (VSPORT). Layer 1 software enables/disables the clock output in order to reduce system power consumption to a minimum if operation of the AD6425 is not required. Figure 6 shows the interface between the AD6426 and the AD6425 as well as to the AD6432 IF chip. Table 12. EVBC Interface Name ...
Page 21
... QRXN VSFS QRXN QRXP DUALBAND RAMP RXON TXON OSEN RXPU TXPU RF FRONT-END RXON TXON GSM_ON DCS_ON GSM_ON DCS_ON DCLK DATA ENB SYNTHESIZERS Figure 6. EVBC and Radio Interface - 21 - AD6426 FREF PAs & TX Control TMX_OUT FILTERS LNA-IN RX RFLO RFLO RFCLK VCOs + Confidential Information ...
Page 22
... Revision Preliminary 2.3 (June 9, ´98) CONTROL), gated with RADIO POWER CONTROL to force a low output when the Radio is off. In order to increase the flexibility of the AD6426, three pins in the Radio Interface are multiplexed with GPO functions. The pins multiplexed are: SYTHEN1, AGCA and AGCB, with the default function being the Radio Interface ...
Page 23
... TXPA WIDTH 2 CC Control Register 76. Bit TXPA WIDTH 1 CC Control Register (9:8) Bit TXPA WIDTH 2 CC Control Register (7: set to zero, then TXPA will be disabled Confidential Information AD6426 BIT is therefore a 10 bit D ) BIT is therefore a 10 bit W ...
Page 24
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) Synthesizer Control The radio interface of the AD6426 supports 2 dynamic synthesizers, with each capable of downloading data on demand. The two Synthesizer Load Dynamic flags located in the ...
Page 25
... Synthesizer Mode Pin Mode (1:0) SYNTHEN0 : 1 The AD6426 provides enable signals for two independent synthesizers. These signals are available at the output pins SYNTHEN0 and SYNTHEN1. The polarities of these signals are individually programmable; i.e. bit Control Register 38 is applied to the synthesizer selected by either bit 2 or bit 1 of the same register ...
Page 26
... Preliminary Technical Information In Modes 2 and 3, PLL programming occurs on any of Rx, Tx and MonEnableEnd through the synthesizer interface. Additionally, AGC programming, controlled via the DSP, is performed during RXON. Table 18. Pin Function in Mode 2 AD6426 Pin Function DSPFLAG0 ô SYNTHEN1 AGCA AGCB DSPFLAG1 The third mode is for support of the Siemens chipset, providing an independent AGC enable from SYNTHEN using the DSP Flag 0 ...
Page 27
... Bypass register for the shortest possible scan path All input activity to the AD6426 will be ignored during this 1 2 time, since all inputs are driven from the preloaded values in the boundary scan chain. Typically therefore this instruction 1 would be preceded by the Sample/Preload instruction ...
Page 28
... ADD17 O 123 GPIO4EN ADD18 O 124 GPIO4 ADD19 O 125 GPIO4 ADD20 O 126 GPIO5EN USCRTS I 127 GPIO5 USCCTSEN B 128 GPIO5 USCCTS O 129 GPIO6EN - 28 - AD6426 # Cell Name I 130 GPIO6 O O 131 GPIO6 I B 132 GPIO7EN B O 133 GPIO7 O I 134 GPIO7 I I 135 CLKIN I B ...
Page 29
... The AD6426 can be switched between two main operating modes, using instructions downloaded via the JTAG interface. This must be done while the AD6426 is held in reset. Once the instruction load is completed the pins are immediately set to reflect the new operating mode. Table 23 shows these modes ...
Page 30
... USC to facilitate testing of the speech transcoder as well as the phone’s acoustic properties. The DAI box interface product is available upon request from Analog Devices. Table 25. DAI Mode AD6426 Pin Function in DAI Mode VSCLK MSCLK VSFS ...
Page 31
... No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98 AD6426 Confidential Information ...
Page 32
... PBGA Package Storage Temperature Range .......................... -65°C to +150°C Maximum Junction Temperature ................................ +150°C Q Thermal Impedance..............................................30°C/W JA Lead temperature, Soldering Vapor Phase (60 sec)........................................... +215°C Infrared (15 sec).................................................. +220°C = +25°C unless otherwise stated AD6426 General Units Comments +85 °C 3.3 Volt 3 ...
Page 33
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) Min CLKIN +2.1V Figure 13. Clock Input CLKOUT Figure 14. Clock Output - 33 - AD6426 Clocks Typ Max Units 76 76 ...
Page 34
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) t 10a t 12a 10b t 12b Figure 15. Memory Interface Timing - 34 - AD6426 Memory Interface Min Max Units 158 ns 162 ns 129 ...
Page 35
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98 n-2 t 42b n-2 t 42b Figure 16. Synthesizer Interface Timing - 35 - AD6426 Radio Interface Min Max Units 152 615 ns 76 307 ...
Page 36
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) Min 8.3 8 Figure 17. High Speed Logging Interface - 36 - AD6426 High Speed Logging Interface Typ Max Units 25 Confidential Information ...
Page 37
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) Min 100 Figure 18: Data Interface Timing - 37 - AD6426 Data Interface Typ Max Units ns 100 Confidential Information ...
Page 38
... No responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) Min Typ 200 Confidential Information AD6426 Test Interface Max Units ns 120 ns 120 ns ...
Page 39
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98 Figure 19. EVBC Interface ASPORT Timing - 39 - AD6426 EVBC Interface ASPORT Min Typ Max 384 ...
Page 40
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98 D15 D14 Figure 20. EVBC Interface BSPORT Timing - 40 - AD6426 EVBC Interface BSPORT Min Typ Max 76 D15 D14 Confidential Information ...
Page 41
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98 D15 D14 t 95 D15 D14 Figure 21. EVBC Interface VSPORT Timing - 41 - AD6426 EVBC Interface VSPORT Min Typ Max Units 76 D13 Confidential Information ...
Page 42
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) Min 462 462 t 101 Figure 22. Parallel Display Interface Timing - 42 - AD6426 Parallel Display Interface Typ Max Units ...
Page 43
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) Min t 103 // t 107 // 105 Figure 23. Serial Display Interface - 43 - AD6426 Serial Display Interface Typ Max Units * 0. 103 ...
Page 44
... VDDRTC (CPDO) SIMDATAOP 103 PWRON (CPDI) SIMCLK 104 SYNTHEN1 SIMCARD 105 SYNTHEN0 TCK 106 SYNTHDATA TMS 107 SYNTHCLK TDO 108 AGCA - 44 - AD6426 # Pin Name 109 AGCB 110 TXPA 111 CALIBRATERADIO 112 RADIOPWRCTL 113 TXENABLE 114 GND 115 CLKIN 116 VDD 117 ...
Page 45
... ADD0 GND J4 DATA14 ADD8 J5 DATA7 DISPLAYCS J6 DATA2 BSDO J7 GPIO1 VDDRTC J8 SIMCLK GPIO2 J9 TMS BSCLK J10 EEPROMCLK ASOFS J11 VSFS ASCLK J12 VSDI - 45 - AD6426 # Pin Name K1 GND K2 ROMCS K3 DATA10 K4 DATA9 K5 VDD K6 DATA6 K7 GND K8 VDD K9 SIMRESET K10 EEPROMEN K11 EEPROMDATA K12 GND L1 DATA15 ...
Page 46
... No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Revision Preliminary 2.3 (June 9, ´98) AD6426 TOP VIEW (PINS DOWN) Figure 24: LQFP Pin Locations - 46 - AD6426 109 108 AGCA SYNTHCLK SYNTHDATA SYNTHEN0 SYNTHEN1 ...
Page 47
... TOP VIEW (PINS DOWN MILLIMETERS MIN TYP MAX MIN 1.60 0.05 0.15 0.002 1.35 1.40 1.45 0.053 21.80 22.00 22.20 0.858 19.90 20.00 20.10 0.783 0.5 0.6 0.75 0.019 0.50 0.17 0.22 0.27 0.007 0. AD6426 109 108 INCHES TYP MAX 0.063 0.006 0.055 0.057 0.866 0.874 0.787 0.791 0.024 0.030 0.020 0.009 0.011 0.003 Confidential Information ...
Page 48
... A1 A MILLIMETERS TYP MAX MIN 1.65 1.80 0.05591 0.40 0.50 0.01181 0.90 0.97 0.02953 13.00 13.15 0.50590 11.00 BSC 10.75 11.55 0.39173 13.00 13.15 0.50591 11.00 BSC 10.75 11.55 0.39173 0.55 0.65 0.17716 0.35 0.43 0.01063 1.00 BSC 0.15 0.20 0. AD6426 0.10 D1 ccc C // INCHES TYP MAX 0.06496 0.07087 0.01575 0.01968 0.03543 0.03819 ...
Page 49
... AD6426 Data Sheet Change Summary Number Date Description of Change 1 5/19/98 Motorola Serial Display mode added. 2 5/19/98 TXENABLE NMI function freeing up the IRQ6 pin added. 3 5/19/98 Dimensional tolerances for BGA package outline drawing added. 4 5/19/98 Memory I/F timing specs separated into characteristics and requirements. 5 5/19/98 Dual band control signals renamed- BANDSELECT0 is multiplexed with GPIO[2], BANDSELECT1 is multiplexed with GPIO[1] ...
Page 50
... Absolute Max ratings broken out separately for PBGA package. 22 2/26/98 Control Processor Data setup time changed from ns. 23 2/26/98 Radio interface section: a reference to the TTP/Hitachi radios added “AD6426 Radio Interface supports radio architectures based on Siemens, Philips, and TTP/Hitachi RF chipsets”. 24 2/27/98 Pin Functionality: OSC13MON pin moved from RTC section to general section. 25 2/27/98 Memory interface timing diagram replaced with one used in 6422 data sheet ...