AD6426 Analog Devices, AD6426 Datasheet - Page 23
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AD6426
Manufacturer Part Number
AD6426
Description
Enhanced GSM Processor
Manufacturer
Analog Devices
Datasheet
1.AD6426.pdf
(50 pages)
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GPIO6 - VBIAS
This general purpose I/O pin can be used to control the
powering up/down of a separate voltage converter, which may
be needed to provide the supply voltage for GaAs RF Power
Amplifiers. Significant turn-on time of the voltage converter
requires an early power-up signal, which is provided by
GPIO6. This control is achieved entirely through a software
driver, without hardware support. Since this function is not
needed for all radio solutions, the GPIO pin can be used for
other functions if not required.
GPIO7 - ANTENNASELECT
This general purpose I/O pin can be used to switch between
two different antennas, as required, when the mobile radio is
used in conjunction with a car-kit with external antenna. This
control is achieved entirely through a software driver, without
hardware support. Since this function is not needed for all
radio solutions, the GPIO pin can be used for other functions if
not required.
Tx Timing Control
The following 5 radio interface pins serve different functions
depending on the radio architecture:
TXPHASE
The purpose of this signal is to switch PLLs between Rx and
Tx modes. The signal is generated under control of the flags
TXPHASE Enable and TXPHASE Polarity of the RADIO
CONTROL CC Control Register 2.
In radios based on the TTP/Hitachi solution, this signal can be
used to switch the VCO´s.
In radios based on the Siemens or Philips solution, this signal
can be used for control switching PLLs, or band switching
UHF PLLs.
TXENABLE
This signal enables the RF modulator and transmit chain
including the PA, and controls the TXON-pin of the AD6425.
The signal is generated under control of flag Transmit Enable
of the RADIO CONTROL CC Control Register 2.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
Preliminary Technical Information
Bit
6
3
0
RADIO CONTROL CC Control Register 2
TXPHASE Polarity
Controls the polarity of the output TXPHASE.
When set to 1, TXPHASE is active low;
When set to 0, TXPHASE is active high.
TXPHASE Enable
Enables the output pin TXPHASE if set to 1.
Transmit Enable
Enables the output pin TXENABLE if set to 1.
- 23 -
TXPA
This signal is used as a power amplifier (PA) enable and/or as
a control signal for the PA control loop. This allows the PA to
be isolated from the supply outside the Tx-slot to save current.
In the PA control loop it can be used to control the dynamics
of the loop. The flag Tx Pa Polarity in the TRAFFIC MODE
CC Control Register 6, provides independent control for the
TXPA signal.
TXPA is derived from the leading edge of TXENABLE signal
shown in Figure 7.
The parameter T
accommodate the EVBC settling time. T
value, accessed via the TXPA OFFSET 1 CC Control Register
73 and the TXPA OFFSET 2 CC Control Register 74.
The parameter T
which defines the PA enable time. T
value, accessed via the TXPA WIDTH 1 CC Control Register
75 and the TXPA WIDTH 2 CC Control Register 76.
If T
1 : 0
7 : 0
1 : 0
7 : 0
TXENABLE
Bit
Bit
Bit
Bit
Bit
7
W
is set to zero, then TXPA will be disabled.
TXPA
TRAFFIC MODE CC Control Register 6
Tx Pa Polarity;
active high, when reset
TXPA OFFSET 1 CC Control Register 73
TD (9:8)
TXPA OFFSET 2 CC Control Register 74
TD (7:0)
TXPA WIDTH 1 CC Control Register 75
TW (9:8)
TXPA WIDTH 2 CC Control Register 76
TW (7:0)
D
W
Figure 7. Timing of TXPA
is a programmable delay (0 to 1023 Q
is a programmable width (0 to 1023 Q
T
D
Confidential Information
T
W
W
is therefore a 10 bit
D
is therefore a 10 bit
AD6426
BIT
BIT
) to
)