AD6426 Analog Devices, AD6426 Datasheet - Page 7
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AD6426
Manufacturer Part Number
AD6426
Description
Enhanced GSM Processor
Manufacturer
Analog Devices
Datasheet
1.AD6426.pdf
(50 pages)
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OVERVIEW
The GSM air interface has been formulated to provide high
quality digital mobile communication. As well as supporting
the traffic channels (speech and/or data), the air interface
specifies a number of signaling channels that are used for call
set up and communications between the network infrastructure
and the mobile. These signaling channels provide the mobile
specific features such as handover, as well as a number of
other intelligent features.
The GSM system closely follows the OSI 7-layer model for
communications. Specifically, GSM defines Layers 1, 2 and 3
of the protocols. The lowest level being Layer 1, or the
Physical Layer. It is this part of the network processing for
which the EGSMP is responsible, performing some of the
Layer 1 functions in dedicated hardware for minimum power
consumption and some in software for increased flexibility.
Layer 1 covers those signal processing functions required to
format the speech/data for transmission on the physical
medium. Data must be structured to allow for identification,
recovery and error correction so that the information can be
supplied error free to the layer 2 sub-systems and to the traffic
sources. In addition, the physical layer processing includes the
timing of both transmit and receive data, the encryption of
data for security purposes and the control of the Radio sub-
system to provide timing and to optimize the radio frequency
characteristics. An object code license to Layer 1 software is
supplied with the AD20msp425 chipset.
FUNCTIONAL PARTITIONING
This datasheet gives only an overview about the functionality
of the EGSMP. The EGSMP consists of three main elements;
the Channel Codec and the Control Processor Sub-System
including several interfaces and the DSP as shown in
1
coding and decoding of traffic and control information. The
Processor Sub-system supports the software functions of the
protocol stack and interfaces with the bus peripheral sub-
systems of the terminal. The DSP performs the channel
equalization and speech transcoding.
Channel Codec Sub-System
The Channel Codec processes data from two principal sources;
traffic and signaling. The former is normally continuous and
the latter determined on demand. Traffic comes in two forms;
speech and user data. The various traffic sources and the
signaling sources are all processed differently at the physical
layer. Speech traffic data is supplied by the speech transcoder
and the remaining data types are sourced from the Control
Processor and interfaced via a dedicated data interface. The
Channel Codec subsystem functional block diagram is shown
in Figure 3.
This Information applies to a product under development. Its characteristics and specifications are subject to change without notice. Analog Devices assumes no
obligation regarding future manufacture unless otherwise agreed to in writing. No responsibility is assumed by Analog Devices for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent
rights of Analog Devices.
Revision Preliminary 2.3 (June 9, ´98)
Preliminary Technical Information
. The Channel Codec is responsible for the Layer 1 channel
Figure
- 7 -
The transmit and receive functions of the Channel Codec are
timed by an internal timebase that maintains accurate timing
of all sub-systems. This timebase is aligned with the on-air
receive signal and all system control signals, both internal and
external, are derived from it.
The physical layer processing can be divided into 4 phases,
two each for up- and downlink. The data in the transmit path
undergoes an ENCODE phase and then a TRANSMIT phase.
Similarly, data in the downlink path is termed the receive data
and it undergoes a RECEIVE phase followed by a DECODE
phase. The buffer between the ENCODE and TRANSMIT
functions is the INTERLEAVE module that holds the data and
permits the building of the transmit burst structure. Similarly
the DEINTERLEAVE module forms the buffer between the
RECEIVE and the DECODE processes.
Each of these four phases is controlled explicitly by the
Control Processor via control registers that define the mode of
operation of each sub-module and the data source they should
process. Typically these control values are updated every
TDMA frame in response to interrupts from the internal
timebase.
The ENCODE process involves the incorporation of error
protection codes. All data is sourced in packets and two forms
of error coding applied; block coding (parity or Fire code) and
convolution coding. The resultant data block is then written to
the INTERLEAVE module where it is buffered in a RAM.
Data is read from the interleave buffer memories contiguously
but written in non-contiguous manner, thereby implementing
the interleaving function. The TRANSMIT process uses a
different time structure now associated with the on-air TDMA
structure. The data is read from the INTERLEAVE module
and formatted into bursts with the requisite timing. This
involves adding fixed patterns such as the tail bits and training
sequence code. The resultant burst is written to the external
Baseband Converter where the modulation is performed and
the output timed to the system timebase before transmission.
INTERFACE
REGISTERS
DSP
Figure 3. Channel Codec Subsystem
INTERFACE
H8
ENCODE
DECODE
DEINTERLEAVE
INTERLEAVE
TIMING AND CONTROL
RADIO / SYNTHESIZER
Confidential Information
ENCRYPT
DECRYPT
AD6426
INTERFACE
INTERFACE
TEST
VBC