MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 106

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MC72000

Manufacturer Part Number
MC72000
Description
Integrated Bluetooth Radio
Manufacturer
Freescale Semiconductor
Datasheet
1
2 Data transferred to TXSR
3
4
TDE status bit/interrupt
Hardware Functional Description
If normal mode is configured to provide more than one time slot per frame, data is transmitted only in the
first time slot. No data is transmitted in subsequent time slots. Figure 71 and Figure 72 show sample timing
of normal mode transfers.
7.4.6.1.1.1
The conditions for data transmission from the SSI in normal mode are as follows:
Figure 71 and Table 52 describe the functions performed during transmit operation in this mode.
106
Rising edge of STFS
Note: A word length frame sync is shown. This
only works if DC>0.
STXD output pin is enabled
the TXSR register appears on the output
Flag status update
Continuous STCK
1. Set the SCSR, STXCR, SCR2, and SOR registers to select normal mode operation, define
2. Enable SSI enabled (SSIEN = 1).
3. Enable TXFIFO (TFEN=1) and configure the transmit watermark (TFWM=n) if this
4. Write data to transmit data register (STX).
5. Enable transmit interrupts.
6. Set the TE bit (TE = 1) to enable the transmitter on the next frame sync boundary.
Valid
TXSR register
Figure 71. Normal Mode Transmit Timing—Continuous Clock (WL=8-bit words, DC=1)
STX register
the transmit clock, transmit frame sync, and frame structure required for proper system
operation.
TXFIFO is used.
STXD
STFS
Normal Mode Transmit
Step
2
Invalid
1
1
6
and the first bit of
Freescale Semiconductor, Inc.
Table 52. Normal Mode Transmit Operations
For More Information On This Product,
MC72000 Advance Information Data Sheet
Go to: www.freescale.com
From STX
The TDE bit is set
Indefinite transition depends on SW interrupt processing
Preliminary
TXFIFO Disabled
(See Figure 71)
7
From TXFIFO
The TFE bit is set if the level of data in the
TXFIFO falls below the watermark level
4
(No Figure Available)
TXFIFO Enabled
MOTOROLA

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