MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 96

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

Hardware Functional Description
RFEN—Receive FIFO Enable
TFEN—Transmit FIFO Enable
RXDIR—Receive Clock Direction
TXDIR—Transmit Clock Direction
SYN—Synchronous Mode
96
Asynchronous Mode
Synchronous Mode
SYN
This control bit enables the FIFO register for the receive section.
This control bit enables the FIFO register for the transmit section.
This control bit selects the direction and source of the clock signal used to clock the receive shift register
(RXSR).
Table 44 shows the clock pin configuration options.
This control bit selects the direction and source of the clock used to clock the TXSR.
Table 44 shows the clock configuration options.
This control bit enables the synchronous mode of operation. In this mode, the transmit and receive
sections share a common clock pin and frame sync pin.
SYN and RXDIR control gated clock mode. The SSI is in gated clock mode when both SYN and
RXDIR are high.
0
0
0
0
1
1
1
1
1 = Allows for eight samples (depending on the receive watermark set in the SFCSR) to be received
0 = FIFO register is not used, and an interrupt request is generated when a single sample is received
1 = A maximum of eight samples can be written to the STX (a ninth sample can be shifting out)
0 = FIFO register is not used.
1 = Clock is generated internally and output to the SRCK pin.
0 = Internal clock generator is disconnected from the SRCK pin and an external clock source can
1 = Clock is generated internally and is output to the STCK pin.
0 = Internal clock generator is disconnected from the STCK pin and an external clock source can
RXDIR
by the SSI (a ninth sample can be shifting in) before the RFF bit is set and an interrupt request
generated when enabled by the RIE bit.
by the SSI (interrupts need to be enabled).
drive this pin to clock the RXSR.
drive this pin to clock the TXSR.
0
0
1
1
0
0
1
1
RXDIR and SYN must both be high for the SSI to be in gated clock mode.
TXDIR
0
1
0
1
0
1
0
1
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
RFDIR
Table 44. Clock Pin Configuration
0
0
1
1
x
x
x
0
Go to: www.freescale.com
TFDIR
0
1
0
1
0
1
x
x
Preliminary
NOTE:
RFS out
RFS out
RFS in
RFS in
SRFS
GPIO
GPIO
GPIO
GPIO
TFS out
TFS out
TFS in
TFS in
FS out
STFS
GPIO
GPIO
FS in
RCK out
RCK out
RCK in
RCK in
SRCK
GPIO
GPIO
GPIO
GPIO
MOTOROLA
Gated out
TCK out
Gated in
TCK out
TCK in
TCK in
CK out
STCK
CK in