MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 72

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

Reset
Reset
W
R
Hardware Functional Description
7.3.7.5 CSPI Test Register (TESTREG)
TESTREG is a 32-bit register that controls how the serial peripheral interface operates and reports status.
The high 16 bits are reserved bits and are always read as 0.
TEST—Test
LOOP—Internal Loop Back
INIT—Initialize State Machine and Edge Detect
SYN—Synchronous Transfer
SSTATUS[3:0]—State Machine Status
72
TEST LOOP INIT
This bit is used for test purposes only.
This bit is used for test purposes only.
This bit field indicates the state machine status. These bits are used for test purposes only.
31
15
0
0
1 = Sample period counter increment value set to 0x0421
0 = Sample period counter increment value set to 0x1
1 = Internal loop back enabled
0 = Internal loop back disabled
30
14
0
0
= Unimplemented or Reserved
SSTATUS[3:0]
29
13
0
0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
SYN
28
12
0
0
Freescale Semiconductor, Inc.
Figure 40. CSPI Test Register (TESTREG)
For More Information On This Product,
MC72000 Advance Information Data Sheet
27
11
0
0
Table 33. SSTATUS[3:0] Encoding
SSTATUS[3:0]
Register address: Base + 0x10
26
10
WAITCNT2
0
0
WAITCNT
CK2SSB1
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Function
ACTIVE
READY
EXCH
BUSY
SSB0
SSB1
IDLE
T2
T3
25
0
9
0
Preliminary
24
Reserved
0
8
0
waiting for EXCH or SLAVE_ENABLE
Waiting for DATAREADY_B
Set SS_B active
SS_B output low to first SPI_CK edge
Delay SPI_CK edge
Start data
Count data bits
Last SCLK edge to SS_B output high delay
Insert SS_B high value
Slave Select is disabled
SS_B output pulse width
Wait for DATAREADY_B active
23
0
7
0
RXCNT[3:0]
22
0
6
0
Description
21
0
5
0
20
0
4
0
19
0
3
0
TXCNT[3:0]
18
0
2
0
MOTOROLA
17
0
1
0
16
0
0
0