MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 113

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

The operation of clearing the TE bit disables the transmitter after completion of transmission of the current
data word. Setting the TE bit again enables transmission of the next word. During the time that TE=0, the
STXD signal is tri-stated. The TE bit should be cleared after the TDE bit is set to ensure that all pending
data is transmitted.
To summarize, the network mode transmitter generates interrupts every time slot (unless the TSM registers
are used) and requires the DSP program to respond to each time slot. These responses may be one of the
following:
7.4.6.1.2.2
The receiver portion of the SSI is enabled when both the SSIEN and the RE bits in the SCR2 are set.
However, when the RE bit is set, the receiver is enabled only after detection of a new frame boundary.
Software has to find the start of the next frame (by checking the RFS bit in the SCSR register). A normal
start-up sequence for receive operation is to do the following steps:
MOTOROLA
Note
1
2
3
4
5
•
•
•
1. Set the SCSR, SRXCR, SCR2, and SOR registers to select network mode operation, define
2. Enable SSI (SSIEN = 1).
STX/STSR
Write the data register with data to enable transmission in the next time slot.
Write the time slot register to disable transmission in the next time slot.
Do nothing—transmit underrun occurs at the beginning of the next time slot and the previous data
is re-transmitted.
the receive clock, receive frame sync, and frame structure required for proper system
operation.
Source
register
register
Signal
TXSR
STFS
Network Mode Receive
Destination
TDE status
STXD pin
interrupt
flag and
register
Signal
TXSR
Table 56. Notes for Transmit Timing in Figure 74
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
Example of a 5 time-slot frame, transmitting in time-slots 0 and 3.
Example with word-length frame sync and standard timing (TFSI=0, TFSL=0,
TEFS=0). Frame timing begins with the rising edge of STFS.
This flag is set at the beginning of each word to indicate that another data word
should be supplied by the software. If the transmit interrupt is enabled, the
processor is interrupted to request the data. The flag (and interrupt) are cleared
when data is written to either the STX or STSR registers (see Section 7.4.9.2,
“Description of Interrupt Operation” for a complete description of interrupt
processing).
On each word clock boundary a decision is made concerning what to transmit on
the next time-slot.
If the STSR register was written during the previous time-slot, the STXD pin is tri-
stated. If the STSR register was NOT written during the previous time-slot, the
contents of the STX register is transferred to the TXSR register and this data is
shifted out. If the STX register has not been written in the previous time-slot, the
previous data is reused.
If neither of these registers were written in the previous time-slot, the TUE status
bit will be set and the hardware will operate as if the STX register had been written.
The STXD pin will be enabled and the contents of the STX will be transmitted
again. Note that this may lead to drive conflicts on the transmit data line.
On active time-slots, the TXSR register contents are shifted out on the STXD pin,
one bit per rising edge of STCK.
On inactive time-slots, the STXD pin is tri-stated so it can be driven by another
device.
Go to: www.freescale.com
Preliminary
Description
Hardware Functional Description
113