MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 76

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

Freescale Semiconductor, Inc.
Hardware Functional Description
As the byte shifts out on the MOSI pin of the master, another byte shifts in from the slave on the master’s
MISO pin. The transmission ends when the receive FIFO full bit, RF, becomes set. Software clears the RF
bit by reading the RX data register.
7.3.8.4 Slave Mode Operation
The CSPI operates in slave mode when the MODE bit is clear. In slave mode, the SPI_CK pin is the input
for the serial clock from the ARM7. Before a data transmission occurs, the SS_B pin of the slave CSPI must
be at logic zero. SS_B must remain low until the transmission is complete.
If the CSPI is configured as slave, the user can set the CSPI control register to match the external CSPI
master’s setting for PHA and POL. SS_B becomes an input signal and is used for capturing data in the
internal receive shift register and for loading data to the internal transmit data shift register. This also
increments the TXFIFO and RXFIFO.
In a slave CSPI module, data enters the shift register under the control of the serial clock from the master
CSPI module. After a word enters the shift register of a slave CSPI, it transfers to the receive FIFO data
register, and the receive FIFO count is incremented. To prevent an overflow condition, slave software then
must read the receive data FIFO register before another full word enters the shift register.
The maximum frequency of the SPI_CK for a CSPI configured as a slave must be less than one-fourth the
bus clock speed. The frequency of the SPI_CK for a CSPI configured as a slave does not have to correspond
to any CSPI baud rate. The baud rate only controls the speed of the SPI_CK generated by a CSPI configured
as a master. Therefore, the frequency of the SPI_CK for a CSPI configured as a slave can be any frequency
less than one-fourth the bus speed.
When the master CSPI starts a transmission, the data in the slave shift register begins shifting out on the
MISO pin. The slave can load its shift register with a new word for the next transmission by writing to its
transmit data FIFO register. The slave must write to its transmit data FIFO register at least eight bus cycles
before the master ends the last word transmission. Otherwise, the word already in the slave shift register
shifts out on the MISO pin.
7.3.9 Timing Diagrams
t5
t1
t2
SS_B
t4
t3
DATAREADY_B
SPI_CK, MOSI, MOSI
Figure 44. Master CSPI Timing Using DATAREADY_B Edge Trigger
76
MC72000 Advance Information Data Sheet
MOTOROLA
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