MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 95

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

RE—Receive Enable
TE—Transmit Enable
MOTOROLA
If the transmit FIFO is enabled:
The TDE bit always indicates the STX register empty condition, even when the transmitter is disabled
by the transmit enable (TE) bit in the SCR2. Writing data to the STX or STSR clears the TDE bit, thus
clearing the interrupt. Two transmit data interrupts with separate interrupt vectors are available: transmit
data with exception status and transmit data without exceptions. Table 43 shows the conditions under
which these interrupts are generated and lists the interrupt vectors.
This control bit enables the receive portion of the SSI.
It is recommended to clear this bit when clearing SSIEN.
This control bit enables the transfer of the contents of the STX register to the transmit shift register
(TXSR) and also enables the internal gated clock.
The normal transmit enable sequence is to write data to the STX register or to the STSR before setting
the TE bit. The normal transmit disable sequence is to clear the TE bit and the TIE bit after the TDE bit
is set.
When an internal gated clock is being used, the gated clock runs during valid time slots if the TE bit is
set. If the TE bit is cleared, the transmitter continues to send the data currently in the TXSR until it is
empty. Then the clock stops. When the TE bit is set again, the gated clock starts immediately and runs
during any valid time slots.
This bit should be cleared when clearing SSIEN.
1 = An interrupt is generated when the TFE flag (in the SCSR) is set
0 = No interrupt is generated
1 = Receive portion of the SSI is enabled and receive data will be processed starting with the next
0 = Receiver is disabled by inhibiting data transfer into the SRX
1 = On the next frame boundary, the transmit portion of the SSI is enabled.
0 = Transmitter continues to send the data currently in the TXSR and then disables the transmitter.
When this interrupt occurs, up to eight values can be written to the STX, depending on the level
of the TXFIFO watermark.
receive frame sync
If data is being received when this bit is cleared, the rest of the word is not shifted in nor is it
transferred to the SRX register. If the RE bit is re-enabled during a time slot before the second
to last bit, then the word will be received.
With internally generated clocks, the frame boundary will occur within a word time. If the TE
bit is cleared and then set again during the same transmitted word, the data continues to be
transmitted. If the TE bit is set again during a different time slot, data is not transmitted until
the next frame boundary.
The serial output enable signal is disabled and any data present in the STX register is not
transmitted. In other words, data can be written to the STX register with the TE bit cleared, and
the TDE bit is cleared but data is not transferred to the TXSR.
Transmit Data with Exception Status
Transmit Data (without exception)
1.See Table 37 for a complete list of interrupts.
Interrupt
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
Table 43. SSI Transmit Data Interrupts
Go to: www.freescale.com
Preliminary
TIE
1
1
TFEN = 0
TDE = 1
TDE = 1
Selection Control
Hardware Functional Description
1
TFEN = 1
TFE = 1
TFE = 1
TUE
1
0
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