MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 69

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

SPIEN — CSPI Module Enable
XCH—Exchange
SSPOL — SS_B Polarity Select
SSCTL — SS_B Wave Form Select
PHA—Phase
POL—Polarity
BITCOUNT[3:0]—Bit Count
MOTOROLA
This bit enables the serial peripheral interface. This bit must be asserted before an exchange is initiated.
Writing a 0 to this bit clears the RX and TX FIFO data and control registers along with the internal
counters and state machine. Changing any of the other CONTROLREG bits, except XCH, when SPIEN
is set is not allowed and may cause the CSPI to enter an invalid state.
In master mode, writing a 1 to this bit triggers a data exchange. This bit remains set while either the
exchange is in progress, or the CSPI is waiting for an active DATAREADY_B input when SPIRDY is
enabled. This bit is cleared automatically when all data in the TXFIFO and shift register is shifted out.
In slave mode, this bit must be clear.
This bit selects the polarity of SS_B signal in both master and slave mode.
This bit selects the output waveform for SS_B signal in master mode.
This bit controls RXFIFO advancement in slave mode.
This bit controls the clock/data phase relationship.
This bit controls the polarity of the SCLK signal.
This bit field selects the length of the transfer. A maximum of 16 bits can be transferred.
In master mode a 16-bit data word is loaded from the TXFIFO to the shift register and only the least n
bits (n = BITCOUNT) are shifted out. The next 16-bit word is then loaded to shift register.
In slave mode when the SSCTL bit is 0 this field controls the number of bits received as a data word
loaded to the RXFIFO. When the SSCTL bit is 1, this field is a don’t care.
Table 32 shows the BITCOUNT[3:0] encoding.
1 = The serial peripheral interface is enabled
0 = The serial peripheral interface is disabled
1 = Initiates exchange (write) or busy (read)
0 = Idle
1 = Active high
0 = Active low
1 = Insert pulse between CSPI bursts
0 = SS_B stays low between CSPI bursts
1 = RXFIFO is advanced by SS_B rising edge
0 = RXFIFO is advanced by BITCOUNT[3:0]
1 = Phase 1 operation
0 = Phase 0 operation
1 = Active low polarity (1 = idle)
0 = Active high polarity (0 = idle)
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
Table 32. BITCOUNT[3:0] Encoding
BITCOUNT[3:0]
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0000
Preliminary
1-bit transfer
Function
Hardware Functional Description
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