MC72000 Freescale Semiconductor, MC72000 Datasheet - Page 58

• Manufacturer Part Number: MC72000
• Description: Integrated Bluetooth Radio
• Manufacturer: Freescale Semiconductor

RST
RST
W
W
R
R
Hardware Functional Description
TXRdy—Transmitter is Causing an Interrupt
RXRDY—Receiver is Causing an Interrupt
RUE—RX FIFO Underrun Error
ROE—RX FIFO Overrun Error
TOE—TX FIFO Overrun Error
58
This read-only bit indicates, while HIGH, that the RXFIFO underrun error occurred. This occurs when
software reads more from the FIFO than is actually present. This bit is updated and valid for each
received character. This bit is set for the last character written to the FIFO indicating that all characters
following this character will be ignored if a write is not performed by software. The RUE bit is cleared
by UART reset or by reading the USTAT register.
This read-only bit indicates, while HIGH, that the RXFIFO ignored data to prevent overwriting the data
in the FIFO. Under normal circumstances, this bit should never be set. It indicates that the user’s
software is not keeping up with the incoming data rate. This bit is updated and valid for each received
character. This bit is set for the last character written to the FIFO indicating that all characters following
this character will be ignored if a read is not performed by software. The ROE bit is cleared by UART
reset or by reading the USTAT register.
This flag bit is set when the UDATA register is filled and ready to transfer to the TXFIFO register and
the register is already full. This error occurs when the software writes more data than is room for in the
FIFO. The transmit data is not transferred in this case. A transmit overrun error does not cause any
interrupts. The TOE bit is cleared by UART reset or by reading the USTAT register.
31
15
0
0
0
0
1 = Interrupt pending
0 = No interrupt
1 = Interrupt pending
0 = No interrupt
1 = Error occurred
0 = No error
1 = Error occurred
0 = No error
1 = Error occurred
0 = No error
= writes have no effect and terminate without transfer error exception
30
14
0
0
0
0
Bits[7:6] are cleared when the respective condition allows it. Status
bits[5:0] are cleared when the register is read.
29
13
0
0
0
0
28
12
0
0
0
0
Freescale Semiconductor, Inc.
For More Information On This Product,
MC72000 Advance Information Data Sheet
27
11
0
0
0
0
26
10
Go to: www.freescale.com
0
0
0
0
USTATBase + $004
25
0
0
9
0
0
Preliminary
NOTE:
24
0
0
8
0
0
TXRD
23
Y
0
0
7
0
RXRD
22
Y
0
0
6
0
RUE
21
0
0
5
0
ROE
20
0
0
4
0
TOE
19
0
0
3
0
FE
18
MOTOROLA
0
0
2
0
PE
17
0
0
1
0
SE
16
0
0
0
0