upd78f0730 Renesas Electronics Corporation., upd78f0730 Datasheet - Page 428
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upd78f0730
Manufacturer Part Number
upd78f0730
Description
8-bit Single-chip Microcontroller
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0730.pdf
(518 pages)
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Notes 1.
428
USB function controller
USBF
Reset function
Low-voltage detector
Interrupt
2.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
Register
RESF
LVIM
LVIS
Table 15-2. Hardware Statuses After Reset Acknowledgment (3/3)
Reset Source
WDTRF bit
LVIRF bit
UF0 EP0 write register (UF0E0W)
UF0 bulk-out 1 register (UF0BO1)
UF0 bulk-out 1 length register (UF0BO1L)
UF0 bulk-in 1 register (UF0BI1)
UF0 device status register (UF0DSTL)
UF0 EPn status register L (UF0EPnSL) (n = 0 to 2)
UF0 address register (UF0ADRS)
UF0 configuration register (UF0CNF)
UF0 interface n register (UF0IFn) (n = 0 to 4)
UF0 descriptor length register (UF0DSCL)
UF0 device descriptor register n (UF0DDn) (n = 0 to 17)
UF0 configuration/interface/endpoint descriptor register n (UF0CIEn)
(n = 0 to 255)
USB function 0 buffer control register (UF0BC)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level selection register (LVIS)
Request flag registers 0L, 0H, 1L, 1H (IF0L, IF0H, IF1L, IF1H)
Mask flag registers 0L, 0H, 1L, 1H (MK0L, MK0H, MK1L, MK1H)
Priority specification flag registers 0L, 0H, 1L, 1H (PR0L, PR0H, PR1L,
PR1H)
External interrupt rising edge enable register (EGP)
External interrupt falling edge enable register (EGN)
Cleared (0)
Cleared (00H)
RESET Input
Preliminary User’s Manual U19014EJ1V0UD
CHAPTER 15 RESET FUNCTION
Hardware
Cleared (0)
Cleared (00H)
Reset by POC
Set (1)
Held
Cleared (00H)
Reset by WDT
Held
Set (1)
Held
Reset by LVI
00H
Undefined
00H
00H
00H
00H
00H
00H
00H
00H
Undefined
00H
00H
00H
00H
FFH
FFH
00H
00H
Undefined
00H
Acknowledgment
Status After Reset
Note 2
Note 2
Note 2
Note 1
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