nt1gt72u89d0by Nanya Techology, nt1gt72u89d0by Datasheet - Page 14

• Manufacturer Part Number: nt1gt72u89d0by
• Description: 240pin Unbuffered Ddr2 Sdram Module With Ecc Based On 128mx8 Ddr2 Sdram D-die
• Manufacturer: Nanya Techology

NT1GT72U89D0BY / NT2GT72U8PD0BY
1GB: 128M x 72 / 2GB: 256M x 72
Unbuffered DDR2 SDRAM DIMM with ECC
Operating, Standby, and Refresh Currents
T
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.
REV 1.0
03/2008
Symbol
I
I
CASE
I
I
I
I
I
I
I
I
DD3PF
DD3PS
I
I
I
DD4W
DD2N
DD2Q
DD3N
DD4R
DD2P
DD0
DD1
DD5
DD6
DD7
= 0 °C ~ 85 °C; V
Operating Current: one bank; active/precharge; t
t
address and control inputs changing once per clock cycle
Operating Current: one bank; active/read/precharge; Burst = 2; t
t
inputs changing once per clock cycle
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE  V
Idle Standby Current: CS  V
t
cycle
Precharge Quiet Standby Current: All banks idle;  is HIGH; CKE is
HIGH; t
bus inputs are floating.
Active Power-Down Current: All banks open; t
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to low (Fast Power-down Exit).
Active Power-Down Current: All banks open; t
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to high (Slow Power-down Exit).
Active Standby Current: one bank; active/precharge; CS  V
CKE  V
inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and
DQS inputs changing twice per clock cycle; CL=2.5; t
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and
DQS outputs changing twice per clock cycle; CL = 2.5; t
I
Auto-Refresh Current: t
Self-Refresh Current: CKE  0.2V
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data changing
at every transfer; t
CK (MIN);
RC (MIN);
CK
OUT
= t
= 0mA
CK (MIN);
CK
IH (MIN);
DQ, DM, and DQS inputs changing twice per clock cycle;
CL=2.5; t
= t
DDQ
CK (MIN)
address and control inputs changing once per clock
IL (MAX);
= V
t
RC
RC
CK
; Other control and address inputs are stable, Data
DD
= t
= t
= t
= 1.8V ± 0.1V (2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs)
RAS (MAX)
RC
t
RC
Parameter/Condition
CK (MIN);
CK
= t
(min); I
= t
IH (MIN);
RFC (MIN)
CK (MIN)
; t
I
OUT
OUT
CK
all banks idle; CKE  V
= t
= 0mA; address and control
= 0mA.
CK (MIN)
CK
CK
; DQ, DM, and DQS
RC
= t
= t
= t
CK (MIN)
CK (MIN)
CK
RC (MIN);
CK
= t
14
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
CK (MIN)
= t
, CKE is
, CKE is
IH (MIN)
IH (MIN);
CK (MIN);
t
CK
RC
=
=
;
PC2-5300
(-3C)
1624
1525
1316
1179
1672
1864
3565
3029
165
921
648
186
311
PC2-6400
(-AD)
1836
1709
1491
1305
1837
2064
3722
3497
172
997
677
313
187
PC2-6400
(-AC)
1836
1709
1491
1305
1837
2064
3722
3497
172
997
677
313
187
© NANYA TECHNOLOGY CORP.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA